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EFW DFB Board-Level Testing Peer Review

EFW DFB Board-Level Testing Peer Review. David Malaspina 2009 Sept 10. Analog Circuitry Verification Plan. (No FPGA processing on 16 KS/s data). (Compare results with specs.). Analyze waveforms in IDL. Signal into DFB Analog Electronics. From ADC to FPGA. FPGA pass data through.

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EFW DFB Board-Level Testing Peer Review

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  1. EFW DFBBoard-Level TestingPeer Review David Malaspina 2009 Sept 10

  2. Analog Circuitry Verification Plan (No FPGA processing on 16 KS/s data) (Compare results with specs.) Analyze waveforms in IDL Signal into DFB Analog Electronics From ADC to FPGA FPGA pass data through Record (raw) waveforms at 16KS/sec (Function Generator) (GSE / Labview) 2

  3. Analog Circuitry Verification Plan • Gains Offsets • Power draw Common mode rejection • Noise Crosstalk • Square wave response Analog filter characterization • Clipping response Temperature variation* response* • *Planned test

  4. FPGA Verification Plan Signal into DFB Analog Electronics From ADC to FPGA FPGA processing FPGA output Compare FPGA, Simulation & IDL results Record (raw) waveforms at 16kHz IDL routines performing same tasks as FPGA IDL formatting of data for ALU module simulation FPGA Simulation 4

  5. FPGA Verification Plan Digital filters Digital filter banks / triggers Field rotation* Defaults load on power up* Spectra* Cross-spectra* Solitary wave counter* Overclocking* *Planned test

  6. Configuration Verification Plan • Verify commanding functionality • Start by testing nominal / default configuration • Can not test every possible configuration (thousands for filter banks alone) • Instead, test each configuration option fully, one at a time (31 possible for filter banks) 6

  7. Configuration Verification Plan S1(10) S2(10) Speed(11) En (2) En(2) Bands(2) E12 DC E12 DC 1/16 S/s On On 7 bins E34 DC E34 DC 1/8 S/s Off Off 13 bins E56 DC E56 DC 1/4 S/s … … … SCM3 SCM3 64 S/s 7

  8. Configuration Verification Plan E12 DC On 7 bins 1/8 S/s E34 DC On S1(10) S2(10) Speed(11) En (2) En(2) Bands(2) E12 DC 1/16 S/s E34 DC Off Off 13 bins E56 DC E56 DC 1/4 S/s … … … SCM3 SCM3 64 S/s 8

  9. Configuration Verification Plan On E12 DC E34 DC E56 DC SCM3 On 1/8 S/s E34 DC 7 bins S1(10) S2(10) Speed(11) En (2) En(2) Bands(2) E12 DC 1/16 S/s Off Off 13 bins E56 DC 1/4 S/s … … … SCM3 64 S/s 9

  10. Example Analog Test Results Input: 4.9 Vpp Sine wave, variable Freq. *Without flight-like matching of caps and resistors

  11. Example Analog Test Results Input: 1 kHz 4.9 Vpp or 9.5 Vpp Sine wave on input channel, all others terminated by 50 ohm resistor. * Results for outdated analog and digital ground plane connection configuration

  12. Example Analog Test Results Input: 1 kHz 1 V square wave 1% overshoot

  13. Example FPGA Test Results Input: 2.4 Vpp Sine wave, variable Freq. *Need to repeat at full range, all channels

  14. END

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