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Hy-C A Compiler Retargetable for Single-Chip Heterogeneous Multiprocessors

This paper discusses a hybrid computing architecture leveraging heterogeneous processors on a single chip. It introduces a retargetable compiler tool designed for efficient partitioning and synthesis across various processing units, including CPUs, FPGAs, and ASICs. Key trade-offs in performance, power consumption, and flexibility are explored, with focus on optimizing resource usage within shared memory configurations. The study includes a detailed analysis of system specifications, performance modeling, and the challenges in implementing and evaluating such multi-processor architectures.

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Hy-C A Compiler Retargetable for Single-Chip Heterogeneous Multiprocessors

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  1. Hy-CA Compiler Retargetable for Single-Chip Heterogeneous Multiprocessors Philip Sweany 8/30/2013

  2. Hybrid Computing • Heterogeneous processors on single chip • “CPU” • FPGA • ASIC • N “CPU”s, M FPGAs, K ASICs • Tradeoffs of performance, power, flexibility

  3. Generic Hybrid Architecture CPU 1 FPGA 1 FPGA 2 CPU 2 Shared Memory CPU m FPGA n Multi-CPU Multi-FPGA

  4. Generic Hy-C Tools Source Code Objectives/Constraints System Specification Partitioning CPU Compiler FPGA Synthesis CPU Power-Performance Model FPGA Power-Performance Model Optimization Control

  5. OMAP Resources (old) Veyron Tesla Shared Memory Ducati Multi-CPU

  6. OMAP Processor Resources • Chiron • 2 x 600 MHz (2 symmetric processors each at 600 MHz with shared L2) • Power 600uW / MHz • Tesla • DSP Sub-System (C64x derivative); 400 MHz, 8-wide ILP • Power 200uW / MHz • Ducati • 200 MHz (targeted for control, low latency code) • Power 100uW / MHz

  7. “Canonical” Resources StrongArm C64x Shared Memory WimpyArm FPGA

  8. “Canonical” Processor Resources • StrongArm • 2 x 600 MHz (2 symmetric processors each at 600 MHz with shared L2) • Power 600uW / MHz • C64x • DSP Sub-System (C64x derivative); 400 MHz, 8-wide ILP • Power 200uW / MHz • WimpyArm • 200 MHz (targeted for control, low latency code) • Power 100uW / MHz • FPGA fabric

  9. Hy-C for Canonical Chip Source Code Objectives/Constraints System Specification Partitioning C64x Wimpy Strong FPGA Optimization Control

  10. Open Issue(s) • How should we describe the architecture? • How should we describe the optimization constraints? • How/when shall we implement this beast? • How will we evaluate the “performance” of the generated code?

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