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Miscellaneous

Miscellaneous. EE116B (Winter 2001): Lecture # Miscellaneous-1. Sizing PMOS/NMOS Inverters. Usual single unloaded inverter guideline: make PMOS and NMOS equal strength to make t pLH =t pHL (W/L) p = m n / m p * (W/L) n = e (W/L) n Situation different when inverters are cascaded.

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Miscellaneous

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  1. Miscellaneous EE116B (Winter 2001): Lecture # Miscellaneous-1

  2. Sizing PMOS/NMOS Inverters • Usual single unloaded inverter guideline: make PMOS and NMOS equal strength to make tpLH=tpHL • (W/L)p = mn/mp * (W/L)n= e (W/L)n • Situation different when inverters are cascaded

  3. Sizing PMOS/NMOS inIdentical Cascaded Inverters • Let (W/L)PMOS be a times larger than (W/L)NMOS • Cdp = aCdn, Cdp = aCdn • CL = (1+a)(Cdn+Cgn)+CW = (1+a) Cn+CW • Propagation delay • tp = (tpLH+tpHL)/2 = const * ((1+a) Cn+CW) * (1+ e/a) where e = mn/mp • Optimal a when dtp/da = 0 • aopt= (e(1+CW/Cn))0.5 = sqrt(e) when CW is neglible Therefore, PMOS should be somewhat smallerthan the e ratio when chaining inverters!

  4. Using Single Inverter as Buffer VDD VDD Buffer Chip Core a ua • Let • tp0 = delay of minimum size inverter when it drives one minimum size inverter • u = the strength of the buffer inverter (i.e. how much larger it is than the minimum) • What is the optimum u? Vout Vin Ci 1 u CL = xCi input capacitance Of minimum-size inverter

  5. Optimum u for Single Inverter Buffer • Total propagation delay tp = utp0 + (x/u) tp0 • Finding optimum u to minimize tp dtp/du = 0  tp0 - (x/u2) tp0 = 0  uopt = sqrt(x) and tp,opt = 2tp0 sqrt(x) It makes sense to introduce a bufferwhen xtp0 > 2tp0 sqrt(x)or, equivalently, when x > 4

  6. VDD u2a u2 Multistage Buffer: N-1 Inverters VDD VDD VDD Chip Core • Propagation delay • tp = u1tp0 + (u2/u1) tp0 + … + (CL/uN-1) tp uN-1a u1a a Vout Vin u1 uN-1 Ci 1 CL = xCi

  7. Optimum u1, u1, … uN-1 forMulti-stage Inverter Buffer • Propagation delay tp = u1tp0 + (u2/u1) tp0 + … + (CL/uN-1) tp0 • Finding optimum u1, u1, … uN-1 to minimize tp tp/ ui = 0 for i = 1, 2, … N-1  tp0 - (u2/u12) tp0 = 0 u2 = u12 (1/u1) tp0 - (u3/u22) tp0 = 0 u3 = u22/u1 = u13 … (1/uN-3) tp0 - (uN-1/uN-22) tp0 = 0 uN-1 = uN-22/uN-3 = u1N-1 (1/uN-2) tp0 - (x/uN-12) tp0 = 0 x = uN-12/uN-2 = u1N Optimum propagation delay is tp = Nu1tp0and, corresponding N = ln(x)/ln(u1)

  8. Optimum N and u1 for Multi-stage Inverter Buffer • Propagation delay tp = Nu1tp0 = u1tp0 ln(x)/ ln(u1) • Finding optimum u1 to minimize tp dtp/du = 0  tp0 ln(x)/ ln(u1) - u1tp0 ln(x)/ u1(ln(u1))2  uopt = e = 2.7182 and tp,opt = e ln(x) tp0 = e ln(CL/Ci) tp0 Optimum buffer design scales consecutivestages in an exponential fashion

  9. Common VHDL IssuesCombinational Processes process (A, B, SELECT)begin if (SELCT=‘1’) then OUT <= A; else OUT <= B; end if;end process; • Sensitivity list must consist of all signals that are read inside the process • Synthesis tools often ignore sensitivity list, but simulation tools do not… a forgotten signal will lead to difference in behavior of the simulated model and the synthesized design

  10. Common VHDL IssuesCombinational Processes process (A, B, SELECT)begin if (SELCT=‘1’) then OUT <= A; else OUT <= B; end if;end process; processbegin if (SELCT=‘1’) then OUT <= A; else OUT <= B; end if; wait on A, B, SEL;end process; • Can use WAIT ON instead of sensitivity list • But not both!

  11. Common VHDL IssuesWait-free Paths processbegin if (some condition) wait on CLK’event and CLK=1; X <= A + B; end if;end process; • Every possible path that the code can take through the process body in a process without sensitivity list must have a WAIT • Otherwise the process can hang (feedback loop)

  12. Common VHDL IssuesMistakenly Inferences Latches process (A,B)begin if (cond1) X <= A + B; elseif (cond2) X <= X – B; end if;end process; • Remember, incomplete assignments imply latches • in the above example, if neither cond1 nor cond2 is true then X will retain its value … basically, X is stored in a latch • if you are writing combinational logic, make sure that every output gets assigned a value along each path (e.g. if statements, case statements) through the process body • in general, latches are not recommended any way in synchronous designs (not testable via scan paths)

  13. Common VHDL IssuesImplicit Register Inference • Storage registers are synthesized for all signals that are driven within a clocked process • Storage registers are also synthesized for all variables that are read before being updated processbegin wait until CLK’event and CLK=1; if (COUNT >= 9) then COUNT <= 0; else COUNT <= COUNT +1; end process; ‘1’ COUNT CLK

  14. Common VHDL IssuesReset (or Set) in Synthesis processbegin wait until CLK’event and CLK=1; if (RST=‘1’) then -- synchronous reset else -- combinational stuff end if; end process; process (CLK, RST)begin if (RST=‘1’) then -- asynchronous reset elsif ( CLK’event and CLK=1) then -- combinational stuff end if; end process; • Must reset all regsiters, other syntehsized chip won’t work • unlike simulation, you can’t set initial values in synthesis! • Asynchronous reset possible only with a process that ha sensitivity list

  15. Common VHDL IssuesCoding Style Influence process(A, B, C, SEL)begin if (SEL=‘1’) then Z <= A + B; else Z <= A + C end if;end process; process(A, B, C, SEL) variable TMP : bit;begin if (SEL=‘1’) then TMP := B; else TMP := C; end if; Z <= A + TMP;end process; • Structure of initially generated hardware is determined by the VHDL code itself • Synthesis optimizes that initially generated hardware, but cannot do dramatic changes • Therefore, coding style matters! B C A B A C + + SEL A + SEL Z Z

  16. Common VHDL IssuesIF vs CASE • IF-THEN-ELSIF-THEN-…-ELSE maps to a chain of 2-to-1 multiplexors, each checking for the successive conditions …if (COND1) then OUT <= X1;elsif (COND2) then OUT <= X2;…else OUT <= Xn;… • CASE maps to a single N-to-1 multiplexor …case EXPRESSION is when VALUE1 => OUT <= X1; when VALUE2 => OUT <= X2; … when others => OUT <= Xn; end case;…

  17. Common VHDL IssuesLet the tool do the Synthesis • Don’t do synthesis by hand! • do not come up with boolean functions for outputs of arithmetic operator • let Synopsys decide which adder, multiplier to use • you will only restrict the synthesis process • Best to use IEEE signed and unsigned types, and convert to integers if needed (IEEE NUMERIC_STD and NUMERIC_BIT packages) example: A_INT <= TO_INTEGER(A_VEC); B_INT <= TO_INTEGER(B_VEC); C_INT <= A_INT * B_INT; C_VEC <= TO_UNSIGNED(C_INT, 4);

  18. Other VHDL Issues • Let synthesis tool decide the numeric encoding of the FSM states • use enumerated type for state • Split into multiple simpler processes • Keep module outputs registered • simplifies timing constraints

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