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WRR ARBITER Final Presentation

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WRR ARBITER Final Presentation

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  1. WRR ARBITERFinal Presentation Students: OferSobel Guy Marcus Supervisor: Moshe Porian 26/10/11

  2. AGENDA • Introduction • Overview • Design • Testing & simulation • SW design • Synthesis • SW & Integration • Documentation • Summary

  3. INTRODUCTION • WRR algorithm arbitrates between clients, requesting usage of the same resource. • Arbitration is performed considering priority weights, assigned to each client. ARBITER

  4. OVERVIEW Project goal: Implementing a WRR ARBITER on an FPGA Requirements: • Generic number of clients (1 to 4) • Communication with host via UART protocol • Real-Time configurable arbitration weights • Interaction with switches and LEDs • 60 MHZ system clock (generated from board’s 50MHz clock) • Automated and textual test environment • Real time performance report to host

  5. TOP LEVEL DESIGN

  6. COMMUNICATION MODULE START TYPE TYPE ADDRESS ADDRESS LENGTH LENGTH DATA Start bit Data Parity Stop bit CRC DATA END

  7. ARBITER MODULE

  8. ARBITER MODULE

  9. ARBITER MODULE

  10. ARBITRATION FLOWCHART Arbiter enable No grant Client/s requesting Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no yes yes Grant Next*requesting client Next* = lowest ID higher than current (up-to clients-num), otherwise lowest ID

  11. ARBITRATION STATE-MACHINE (3 CLIENTS) P1 1 P2 P3 P1 None P2 P3 P3 P3 P1 P2 2 3 P1 P2

  12. ARBITRATION EXAMPLE(3 CLIENTS) Arbiter enable 1 No grant Client/s requesting 0 Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no 2 3 1 2 3 yes yes Grant Next* requesting client

  13. ARBITRATION EXAMPLE(3 CLIENTS) Arbiter enable 1 No grant Client/s requesting 0 Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no 2 3 1 2 3 yes yes Grant Next* requesting client

  14. ARBITRATION EXAMPLE(3 CLIENTS) Arbiter enable 1 No grant Client/s requesting 0 Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no 2 3 1 2 3 yes yes Grant Next* requesting client

  15. ARBITRATION EXAMPLE(3 CLIENTS) Arbiter enable 1 No grant Client/s requesting 0 Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no 2 3 1 2 3 yes yes Grant Next* requesting client

  16. ARBITRATION EXAMPLE(3 CLIENTS) Arbiter enable 1 No grant Client/s requesting 0 Grant requesting client with lowest ID no Granted client stopped requesting Time’s up! Other client/s requesting ? Other client/s requesting ? Keep granting same client no 2 3 1 2 3 yes yes Grant Next* requesting client

  17. TESTING & SIMULATION Simulation environment characteristics: • Mentor Graphics Modelsim 6.3C • Automated testing – • Textual input files • Test logs • Batches of tests • Arbitration golden model reference • Test-benches fitted for specific modules – • Communication module TB • Peripherals TB • Arbiter module TB • Top TB

  18. COMMUNICATION MODULE TESTING MSG RPLY RPLY MSG WR MSG CTRL RD REQ RD MSG WR MSG RD MSG ARB RD REQ 1. Messages types test

  19. COMMUNICATION MODULE TESTING X X X RX ERR RX ERR RPLY (unchanged) Invalid WR MSG RD MSG Invalid RD MSG Messages types test UART errors test

  20. COMMUNICATION MODULE TESTING X X X X DEC ERR RBM ERR Invalid MSG Invalid MSG START byte TYPE byte CRC byte END byte Messages types test UART errors test Message errors test ADDRES byte (write permission) ADDRESS byte (false CS) LENGTH byte (write permission)

  21. PERIPHERALS TB 50 MHz 60 MHz LOCK SYS RST (low pulse) SYS RST low SYS RST high SYS RST low SYS RST high 60 MHz INT RST (low pulse) EXT RST high EXT RST low EXT RST high SYNC

  22. ARBITER MODULE TB Write random values Write (“FF”) RESET RESET Read RO registers Read (“00”) Read back Read back Read (“00”) Reset & Registers test

  23. ARBITER MODULE TB Specific weights Arbiter enable Random TICK len Request all GRANTS Arbiter enable Random TICK len Specific weights Specific weights Arbiter enable Random TICK len GRANTS GRANTS Read history Request all Request all GRANTS compare Reset & Registers test Arbiter steady state test Process repeats for all requests combinations and various weights

  24. ARBITER MODULE TB Specific weights Arbiter enable Set TICK len Change requests Set requests GRANTS Specific weights Specific weights Set TICK len Set TICK len Arbiter enable Arbiter enable GRANTS GRANTS Set requests Change requests Read history Set requests Change requests Reset & Registers test Arbiter steady state test Dynamic arbitration test Process repeats for various request vectors, for the following weights: all ‘0’, all equal (>0), unequal

  25. ARBITER MODULE TB Random weights Req pulse 1 cycle Req low pulse 2 cy Requests “00” Set TICK len Arbiter enable Req pulse 2 cycles Req low pulse 1 cy Req pulse 6 cycles Requests all GRANTS GRANTS unchanged Random weights Set TICK len Arbiter enable GRANTS unchanged GRANTS X X Reset & Registers test Arbiter steady state test Dynamic arbitration test Filter test filter_depth_g = 5 De-met_enable_g = ‘true’ Process is symetric to the 1st part of the test… Repeat process up to a pulse of 5 clock cycles

  26. ARBITER MODULE TB Set weights Change weights Arbiter enable Set TICK len Requests all GRANTS GRANTS update Set TICK len Arbiter enable Arbiter enable Set weights Set weights Set TICK len Changeweights GRANTS GRANTS Changeweights GRANTS update GRANTS update Requests all Read history Read history Requests all Reset & Registers test Arbiter steady state test Dynamic arbitration test Filter test Repeat for various weights 5. Configuration switch test

  27. ARBITER MODULE TB Set random TICK len Randomize requests Set random weights Arbiter enable GRANTS Arbiter enable Set random TICK len Set random TICK len Set random weights Set random weights Arbiter enable GRANTS GRANTS Reset & Registers test Arbiter steady state test Dynamic arbitration test Filter test Repeat for 15 iterations of random weights Configuration switch test Random arbitration test

  28. TOP TB TICK messages Status RPLY RPLY Request all Read CTRL REGS Read ARB REGS Enable Arbiter Adjust TICK Configure ARB REGS Configure golden model RSET HS Request all Request all Top messages test

  29. TOP TB RBM error message Status (RX error) DEC error message RX error message Status (RX err) Status (no err) Status WR MSG with parity err Clear errors WR MSG with parity err WR MSG with start byte err unMask errors Clear errors Read status Read status Clear errors Mask errors WR MSG with addr byte err Read CTRL status RSET HS Top messages test Top error test No error message is to be received

  30. TOP TB RPLY (“00”) Status Status WR MSG to Arbiter module RD REG from Arbiter module Internal reset HS RSET HS Top messages test Top error test Top reset test

  31. TOP TB TICK messages Status Enable TICK messages Randomize requests Set TICK length Set TICK length Request all Set weights Set weights Enable Arbiter RSET HS Grants Grants Grants Request all Request all Top messages test Top error test Top reset test Top Golden model test

  32. SYNTHESIS RESULTS • Synthesis successful with clock at 60Mhz.

  33. SYNTHESIS RESULTS • No timing violations.

  34. SW & INTEGRATION

  35. GENERIC WRR ARBITER CODE GENERATION • The Arbiter component RTL code can be generated for any number of clients using the shared resource (integer 2 to ∞). • Code is generated using a matlab GUI.

  36. DOCUMENTATION • Version control using the faculty SVN server • Design documents: • Specification document • Test plan document • HW/ SW interface document

  37. SUMMARY • Deviation from preliminary specifications: • Generality of client number • Generality of UART bit number • Referenced blocks: • uart_receiver (from RunLen project) • reset_block sub-blocks (from RunLen project) • crc_generator (from www.ElectronicDesignworks.com) • pll (AlteraMegaFunction)

  38. SUMMARY (cont’d) • Project highlights: • Full system design (VHDL, Verification, Synthesis, SW and integration) • Autonomous component (and not “just a core”) • Very easy integration thanks to a thorough verification phase • Coding guidelines – synthesis oriented, flexibility oriented, well documented