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WRR ARBITER Mid-term Presentation

WRR ARBITER Mid-term Presentation. Students: Ofer Sobel Guy Marcus Supervisor: Moshe Porian. 11/1/11. Project Goal. Implementing a WRR ARBITER on an FPGA Implementation will be to Altera Cyclone® II 2C35 FPGA located on an Altera DE2 board. Project steps.

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WRR ARBITER Mid-term Presentation

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  1. WRR ARBITERMid-term Presentation Students: OferSobel Guy Marcus Supervisor: Moshe Porian 11/1/11

  2. Project Goal Implementing a WRR ARBITER on an FPGA Implementation will be to Altera Cyclone® II 2C35 FPGA located on an Altera DE2 board

  3. Project steps • Determining specifications • Architecture characterization • Conceptual design • VHDL implementation • Verification • Synthesis • Real-Time testing

  4. Top level design

  5. RX PATH – detailed view

  6. TX PATH – detailed view

  7. CONTROLLER MODULE– detailed view

  8. ARBITER MODULE– detailed view

  9. Arbitration FSM

  10. Arbitration FSM

  11. Arbitration FSM

  12. Arbitration FSM

  13. Arbitration FSM

  14. Arbitration - wave • Tick time: every 5 clocks • Weights: • Filtered requests

  15. Arbiter features • External/ internal request muxing • Grant history tracking • Status message initiation

  16. Testability Tested modules: • RX Path • TX Path • Controller and Peripherals • Arbiter module • Top

  17. Simulation environment

  18. Simulation environment Input file:

  19. Simulation environment Output Log:

  20. Test Plan (Arbiter Module) • Reset and registers test • Steady state arbitration test • Dynamic arbitration test • Mode test • Filter test • Configuration switch test • Random arbitration test • Functional test

  21. Schedule

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