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Sorting Units for FPGA-Based Embedded Systems

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Sorting Units for FPGA-Based Embedded Systems

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    1. Sorting Units for FPGA-Based Embedded Systems

    2. MOTIVATION

    3. GOALS Development of sorting machines Coupled to an embedded microprocessor Boost the global performance of general embedded applications using sort operations (e. g. databases)

    4. APPROACHES Odd-Even Sorting Network Machine, sorting network Insert Sorting Machine, scalable and linear array. FIFO-based Merge Sorting Machine, FIFO support using BRAMs in FPGAs.

    5. Sorting Networks

    6. SORTING NETWORK

    7. SORTING NETWORK ALGORITM Odd-Even K. Batcher, (1968) Bitonic-sort Merge-Sort Odd-Even Other variations of the Batcher sorting algorithms have been proposed without significant improvements

    8. BITONIC MERGE

    9. ODD-EVEN

    10. PROPOSAL Implementation of sorting networks using FPGAs Different implementations can be done: Pipelined ? more hardware, high data throughput Odd-Even Transposition Bitonic-Sort, Merge Odd-Even Sequential ? less hardware, Network split on sequential stages Odd-Even Transposition Two options considered: SN-I, SN-II

    11. SEQUENTIAL (SN-I)

    12. COMPARATOR-SWAP

    13. SWITCH NETWORK

    14. SEQUENTIAL (SN-II)

    15. Insertion sorting

    16. INSERTION SORT: IDEA Each element to sort is inserted in the right position

    17. INSERTION SORT: BLOCK DIAGRAM

    18. FIFO Based Merge Sort

    19. FIFO-Based MERGE SORT

    20. Experimental Results

    21. HARDWARE RESOURCES

    22. SPEED-UP

    23. SPEED-UP simultaneous LOAD/STORE

    24. Conclusions and Future Work

    25. CONCLUSIONS Four sorting machines have been implemented and compared. Hardware resources versus performance are evaluated Best solution results an Hybrid solution between INSERT and FIFO MERGE Speed-Up 1,6..15, related to the quicksort pure software Using parallel load/store (3 or more) the fifo-merge is the fastest machine.

    26. FUTURE WORK Characterization of the sorting machines with more complex FPGAs (Virtex 4 and 5) Histogram based sorting Exploring FPGAs resources BRAMs, SRL, MULTIPLIERS Hash Tables Sorting Sorting for a limited set of elements, also using FPGAs resources

    27. Thanks for your attention!

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