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Ethernet Based Embedded IOC for FEL Control Systems

Ethernet Based Embedded IOC for FEL Control Systems. J. Yan, D. Sexton, Al Grippo, W. Moore, and K. Jordan ICALEPCS 2007 October 19, 2007 Knoxville Convention Center Knoxville, Tennessee USA. JLab FEL Energy Recovered Linac. E = 120 MeV 135 pC pulses up to 75 MHz

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Ethernet Based Embedded IOC for FEL Control Systems

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  1. Ethernet Based Embedded IOC for FEL Control Systems J. Yan,D. Sexton, Al Grippo,W. Moore, and K. Jordan ICALEPCS 2007 October 19, 2007 Knoxville Convention Center Knoxville, Tennessee USA

  2. JLab FEL Energy Recovered Linac E = 120 MeV 135 pC pulses up to 75 MHz 20/120/1 microJ/pulse in UV/IR/THz 250 nm – 14 microns, 0.1 – 5 THz

  3. Motivation • Additional channels for BPM and Viewer systems required • The cost for expanding the current configuration is high • FEL “master plan” is to move away from Crate-Based solutions involvinglicensed software • Use distributed processors instead of VME IOCs • Develop a new I/O connection as a “default” standard • Embedded COTS Arcturus Coldfire Board chosen to start with • Chose RTEMS as the real-time operating system for the IOC

  4. Current VME IOC System

  5. New System Design

  6. Single Board IOC (SBIOC) • Integrated a ColdFire uC5282 Microprocessor with an FPGA • A standard footprint for the embedded IOC • Provide abundant of I/O connectors • Compatible with existing designs • Stand-alone system • Suitable for most of I/O controls • Beam Position Monitor • Beam Viewer & Video controls • Stepper motor controls

  7. Block Diagram of the SBIOC

  8. Pictures of the SBIOC FPGA ColdFire uC5282 13.5 cm 5.5 cm SBIOC Card

  9. Modules on the FPGA

  10. Circuit of the FPGA-ColdFire Bridge

  11. Read and Write Cycles of the Bridge Read Bus Cycles Write Bus Cycles

  12. BPM Applications • The first version of new BPMs have been running for2 years • They are very reliable, and easily maintained • Throughput from the ADC is 100 Hz. This is a limitation • New solution has to be found • Use Single Board IOC to improve the performance • Cut the cost. The cost of original configuration is $3000/BPM; the new system is $1200/BPM

  13. First Version BPM (without FPGA) ColdFire uC5282

  14. New Version BPM * FPGA Functions: • Sampling ADC, Calculations (add & average) • Memory block to save data • Communication with the ColdFire processor * Goal: 100KHz throughput • FPGA clock 20 MHz • ADC 1 MSPS throughput • FPGA sampling frequency up to 2 MHz • ColdFire processor read data through bus

  15. New Version BPM with the SBIOC 4 Channels SBIOC Card

  16. 3U General Purpose Processor Card (GPPC) • A Carrier board that provides a bridge between the SBIOC and other crates • Pin-pin compatible with existing CAN bus Digital Signal Processor (DSP) card. • Use resources from the SBIOC • 96-Pin Backplane • For Beam Viewer Controls, GC magnet power supply, HVPS Controller, Temperature monitoring system, Vacuum instruments.

  17. Block Diagram of the 3U GPPC

  18. 3U GPPC for Beam Viewer Control Beam Viewer Control Card Ethernet 3U General Purpose Processor Card

  19. Software Applications • RTEMS (4.7) Chosen as the real-time operating system for SBIOC • EPICS R3.14 as the development toolkits • Developed the EPICS applications for BPM, 3U GPPC, Beam Viewer control • On-line remote firmware uploading and rebooting • Use Software Altera Quartus II to program the codes for the FPGA

  20. Summary & Conclusions • The first version of BPM based on embedded IOC had been running on FEL. It is reliable, and easily maintained. • Setup the software • EPICS, RTEMS, Device support, Database, MEDM screens • Designed the Single Board IOC and 3U General Purpose Processor Card • ColdFire uC5282 processor is a ideal choice for the embedded IOC • By distributing the IOC on front-end I/O devices, dramatically cut the cost of expensive cables. • It is a novel configuration to use FPGA+uC5282+RTEMS for the FEL diagnostics and controls upgrading

  21. Acknowledgement • Thanks • Eric Norum in Argonne National Lab for providing RTEMS tools and installation instructions. • Trent Allison in EESICS group of Jefferson Lab for the help of Altera FPGA programming. • The Operations and Commissioning team of the FEL for the support and technical advice • This work is supported by the Office of Naval Research, the Joint Technology Office, The Commonwealth of Virginia, the Army Night Vision Laboratory, the Air Force Research Laboratory, and by DOE Contract DE-AC05-84ER40150.

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