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Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012

An Ultra-Low-Voltage CMOS Mixer Using Switched- Tr anscondu ctance Current-Reuse Dynamic-Threshold-Voltage Gain-Boosting Techniques. Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012. Big Picture.

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Amir Hossein Masnadi and Shahriar Mirabbasi IEEE NEWCAS, June 2012

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  1. AnUltra-Low-Voltage CMOS Mixer Using Switched-TransconductanceCurrent-Reuse Dynamic-Threshold-Voltage Gain-BoostingTechniques Amir HosseinMasnadi and ShahriarMirabbasi IEEE NEWCAS, June 2012

  2. Big Picture Designing Building Blocks for Ultra-Low–Voltage/Power CMOS RF Front-End for applications such as: • Biomedical Application Above Picture : Smart Stents, SoC and MEMS lab, UBC • Low Power Wireless Communication

  3. Outline • Overview of Conventional Active Mixers • Overview of techniques • Stack Reduction, LO-Gm Separation • Current-Reuse • Dynamic Threshold • Mixer Design • Gm-Stage - Double Balanced Current Reuse Gilbert Structure • LO -Stage - Switched Supply Voltage • Post-Layout Simulation Results and Comparison • Concluding remarks

  4. Conventional Active Mixers • Gilbert-Type Mixer (Current commutating) • 3 stacked transistors each transistor VDS is around VDD/3 • Considering Vth is around 0.4 V, minimum supply voltage is around 1.2 V • To increase conversion gain (CG) one can increase load (CGαRL×) • Penalty: more voltage drop across load trade-off between VDD and CG • Mixer core is always ON (For Biasing the transistors) Reduce the voltage drop across the Load Resistor to increase M1 drain Voltage Even more challenging if IIP3 has to be improved Challenge of biasing current source in saturation for low supply voltage (e.g. VDD < 1.5) Limitations for Supply-Voltage: Power Consumption issue:

  5. Supply Voltage (V) – Year (1997-2012) • Bulk_Drivenand Folded Methods • Very Low CG (1<CG<9) Roughly Reduction of 0.085 V/Year y = -0.0853x + 172.44 Range of Threshold Voltage

  6. Mixer Power (mW)– Year (1997-2012) y = -0.8847x + 1781 Roughly a reduction of 0.88 mW/Year (it is leveling off)

  7. Design Bottlenecks • Stacked Architectures : For decreasing Supply Voltage we should reduce Number of transistor Stacked stages , we have different methods , below we bring ONLY two of them : • Bulk-Driven Method • Low Conversion Gain (Mostly below 10) • Constant Biasing Current • Folded Gilbert Architecture • Moderate Conversion Gain – Wide Band • Constant Biasing Current • Bulky Inductors • Threshold Voltage : If decreases the headroom will increases, so it would be nice if we have lower threshold Voltage • We can't find any significant publication for reducing threshold voltage in Mixers

  8. Proposed Techniques for Ultra Low Voltage Mixer • Reducing Stacked Transistors by Switched Transconductance: • LO-Stage and Gm-Stage can be separated by switching supply voltage of Gm-Stage • Turn ON & Off Gm-Stage with LO  Save Power Gm ON/OFF Approach Current Commutating Approach

  9. Proposed Techniques for Ultra-Low-Voltage Mixer • Choosing Gm-Stage, Maximizing Conversion Gain and Linearity: Pick a proper Gm-Stage for High Conversion Gain (High output Gm) and High Linearity  Current-Reuse technique • Overal Gm = gmn+gmp • Linearity will be improved Total Gm=gmn Total Gm=gmn+gmp Current-Reuse is similar to Push-Pull Buffer

  10. Switching Stage • We should implement a switch between VDD and GND • Different Options : • Simple Digital Inverter • High-speed comparator (compare LO with GND, requires low LO power) • Inverter with Dynamic Threshold-Voltage: • Reduce VTH of NMOS transistors by connecting inverter output to body of NMOS (DTMOS) Output voltage of the inverter with CL=1pF, PLO= −8 dBm, 2.45 GHz LO signal and DC value of LO is 0.3 V, (a) with dynamic threshold (DTMOS) inverter (b) without DTMOS. .

  11. Proposed Building Block For ULV Mixer

  12. Proposed Double-Balanced Design

  13. Post-Layout Simulation Results • IBM0.13-µm CMOS • VTH≈ 0.42 V

  14. Effect of Dynamic Threshold Technique

  15. Conversion Gain at Different Supply Voltages

  16. Concluding Remarks Techniques to improve mixer performance: • Reducestacked levels • For Gm-Stage , try to choose blocks with higher output Gm and Linearity • Reduce VTH by body effect (Dynamic Threshold Technique), Both for Gm-Stage and LO-Stage, so we can use it for increasing headroom an • Turn-off circuit when you don’t want to use it to save power TSMC 90nm Process • RF LO • IF+ • Active Balun • IF- • Resonator • Buffer • Mixer Core • Resonator

  17. Acknowledgments • NSERC • CMC Microsystems • IBM • TSMC And thank you for listening!

  18. References • E.A.M. Klumperink, S.M. Louwsma, G.J.M. Wienk, and B. Nauta, “A CMOS switched transconductor mixer,“ IEEE Journal of Solid-State Circuits, ­­­vol.39, no.8, pp. 1231- 1240, Aug. 2004. • Hanil Lee; Mohammadi, S., “A 500μW 2.4GHz CMOS Subthreshold Mixer for Ultra Low Power Applications,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp.325-328, 3-5 June 2007. • KihwaChoi; Dong Hun Shin; Yue, C.P., “A 1.2-V, 5.8-mW, Ultra-Wideband Folded Mixer in 0.13-μm CMOS,“ IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, vol., no., pp.489-492, 3-5 June 2007. • Assaderaghi, F.; Sinitsky, D.; Parke, S.A.; Bokor, J.; Ko, P.K.; ChenmingHu; "Dynamic threshold-voltage MOSFET (DTMOS) for ultra-low voltage VLSI ," Electron Devices, IEEE Transactions on , vol.44, no.3, pp.414-422, Mar 1997. • V. Vidojkovic, et al., “A Low-Voltage Folded-Switching Mixer in 0.18-um CMOS, “ IEEE J. Solid-State Circuits, vol. 40, pp. 1259-1264, June 2006.  • S. He and C.E. Saavedra, “An Ultra-Low-Voltage and Low-Power  2 SubharmonicDownconverter Mixer,”  IEEE Transactions on Microwave Theory and Techniques, vol. 60, no. 2, pp. 311-317, Feb. 2012. • M. Huang, et al., "A 5.25-GHz CMOS Folded-Cascode Even-Harmonic Mixer for Low-Voltage Applications," IEEE Trans. Microwave Theory Tech., vol. 54, no. 2, pp. 660-669, Feb. 2006. 

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