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Advanced Detector Controller for the E-ELT: Key Features and Architecture Overview

This presentation discusses the advanced detector controller developed for the E-ELT at the ESO Scientific Detector Workshop 2013. It details two main detectors: the LGSD and NGSD. The LGSD features a large size of 55x45 mm, 1760x1680 pixels, and massive parallel architecture with 70,400 Analog-to-Digital structures. The NGSD is a quarter cut of the LGSD, boasting 88x84 sub-apertures and rapid data conversion capabilities. Key components include advanced FPGA architecture, high-speed output lines, and robust environmental control features.

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Advanced Detector Controller for the E-ELT: Key Features and Architecture Overview

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  1. ESO AO Detector Controller for the E-ELT Javier Reyes, Mark DowningEuropean Southern Observatory, ESO (http://www.eso.org)Jorge Romero University of Málaga (http://www.uma.es) ESO AO Controller for E-ELT Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy

  2. The LGSD detector • Large size detector: 55x45mm • 1760 x 1680 pixels • 88 x 84 SA • 20×20 pixel sub-apertures • Massive parallel architecture • 70,400 Analog-to-Digital structures • 1.4ms, 700 fps nominally • The NGSD detector • NGSD is a quarter cut out of the LGSD • 44 x42 SA • 17600 ADCs • The operation of the two imagers is the same Top view of the NGSD package ESO AO Controller for E-ELT Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy

  3. NGSD Pixel Output Port • Data conversion and serialization is built-in in the imagers • 22 high-speed LVDS output lines • Each LVDS output sends the data from two columns of sub-apertures • NGSD Controller Architecture • Advanced FPGA • Minimal analog circuitry around it, basically DACs for bias generation • 10GbE fiber links • Control PC • Real-Time-Computer ESO AO Controller for E-ELT Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy

  4. NGSD Prototype Controller • Xilinx Virtex-6 VLX240T FPGA • Xilinx Virtex-7 XC7VX690T • No sequencer on-chip so almost all critical clocks driven by the FPGA • Use of Gigabit Ethernet IP core • Some Other Features • Integrated Peltier controller • Temperature, Humidity and Pressure sensors • Over-voltage and Over-Temperature protection • Detector power-up sequencing • Synchronization to other cameras ESO AO Controller for E-ELT Scientific Detector Workshop 2013. 7-11 October 2013. Florence, Italy

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