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Computer Architecture COSC 3430

Computer Architecture COSC 3430. Lecture 3: Instructions. The Instruction Set Architecture. software. instruction set architecture. hardware. The interface description separating the software and hardware. Computer’s Internal Clock. Frequency:

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Computer Architecture COSC 3430

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  1. Computer ArchitectureCOSC 3430 Lecture 3: Instructions

  2. The Instruction Set Architecture software instruction set architecture hardware The interface description separating the software and hardware.

  3. Computer’s Internal Clock • Frequency: • Frequency is number of complete waves passing per unit time. • It is measured in Hertz (Hz), the number of cycles per second. • 1 KHz = 103 Hz. • 1 MHz = 106 Hz. • Series of electrical pulses with fixed interval between pulses (cycle time) • 800 MHZ machine = 800x106 cyc/sec = 1.25x10-9 sec/cyc = 1.25 ns/cyc • Synchronizes all components • Updates state: inputs only change stored values at specific instances • Regulate instruction execution: e.g., 1/clock cycle cycle time time for one full cycle

  4. Operations of the Computer Hardware Chapter 2.2

  5. Assembly Language Instructions • Language of the machine • More primitive than higher level languages e.g., no sophisticated control flow • Very restrictive e.g., MIPS arithmetic instructions • We’ll be working with the MIPS instruction set architecture • similar to other architectures developed since the 1980's • used by NEC, Nintendo, Silicon Graphics, Sony, … Design goals: maximize performance, minimize cost, reduce design time, minimize memory space (embedded systems), minimize power consumption (mobile systems)

  6. RISC - Reduced Instruction Set Computer • RISC philosophy • fixed instruction lengths • load-store instruction sets • limited addressing modes • limited operations • MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC, Intel (Compaq) Alpha, … • Instruction sets are measured by how well compilers use them as opposed to how well assembly language programmers use them

  7. MIPS Arithmetic Instruction • MIPS assembly language arithmetic statement add $t0, $s1, $s2 sub $t0, $s1, $s2 • Each arithmetic instruction performs only one operation • Each arithmetic instruction specifies exactly three operands destination  source1 op source2 • Those operands are contained in the datapath’s register file ($t0,$s1,$s2) • Operand order is fixed (destination first) rd rs rt

  8. Compiling More Complex Statements • Assuming variable b is stored in register $s1, c is stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement h = (b - c) + d rd b c sub $t0, $s1, $s2 add $s0, $t0, $s3 rd b-c d rd rs rt

  9. Operands of the Computer Hardware Chapter 2 section 2.3

  10. Register File 5 5 5 32 32 32 src1 addr src1 data src2 addr 32 locations dst addr src2 data write data 32 bits MIPS Register File • Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file • Holds thirty-two 32-bit registers • With two read ports and • One write port • Registers are • Faster than main memory • Easier for a compiler to use • Can hold variables so that • code density improves (since register are named with fewer bits than a memory location) • Register addresses are indicated by using $

  11. Naming Conventions for Registers 0 $zero constant 0 (Hdware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hdware)

  12. Processor Devices Control Input Memory Datapath Output Registers vs. Memory • Arithmetic instructions operands must be registers, — only thirty-two registers provided • Compiler associates variables with registers • What about programs with lots of variables?

  13. 32 32 32 Processor – Memory Interconnections • Memory is viewed as a large, single-dimension array, with an address • A memory address is an index into the array read addr/ write addr Processor ? locations 232 230 words read data Memory write data 32 bits

  14. MIPS Data Types Bit: 0, 1 Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits (4 bytes) is a word 64 bits is a double-word Character: ASCII 7 bit code Decimal: digits 0-9 encoded as 0000b thru 1001b two decimal digits packed per 8 bit byte Integers:2's complement Floating Point

  15. Byte Addresses • Since 8-bit bytes are so useful, most architectures address individual bytes in memory • Therefore, the memory address of a word must be a multiple of 4 (alignment restriction) • Big Endian: leftmost (MSB) byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: rightmost (LSB) byte is word address Intel 80x86, DEC Vax, DEC Alpha (Windows NT)

  16. little endian byte 0 3 2 1 0 0 1 2 3 big endian byte 0 Addressing Objects: Endianess and Alignment • Big Endian: leftmost byte is word address • Little Endian: rightmost byte is word address msb lsb 0 1 2 3 0 1 2 3 Aligned Alignment restriction: requires that objects fall on address that is multiple of their size. Not Aligned

  17. . . . 0 1 1 0 24 Memory . . . 0 1 0 1 20 . . . 1 1 0 0 16 . . . 0001 . . . 0 0 0 1 12 . . . 0 0 1 0 8 . . . 1 0 0 0 4 . . . 0 1 0 0 0 Data Word Address MIPS Memory Addressing • The memory address is formed by summing the constant portion of the instruction and the contents of the second (base) register lw $t0, 4($s3) #what? is loaded into $t0 sw $t0, 8($s3) #$t0 is stored where? $s3 holds 8 . . . 0001 in location 16

  18. . . . . . . A[3] $s3+12 A[2] $s3+8 A[1] $s3+4 A[0] $s3 Compiling with Loads and Stores • Assuming variable b is stored in $s2 and that the base address of array A is in $s3, what is the MIPS assembly code for the C statement A[8] = A[2] - b lw $t0, 8($s3) sub $t0, $t0, $s2 sw $t0, 32($s3)

  19. Compiling with a Variable Array Index • Assuming A is an array of 50 elements whose base is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement c = A[i] - b add $t1, $s3, $s3 #array index i is in $s3 add $t1, $t1, $t1 #temp reg $t1 holds 4*i add $t1, $t1, $s4 #addr of A[i] lw $t0, 0($t1) sub $s2, $t0, $s1

  20. MIPS Instructions, so far

  21. Review: MIPS Organization • Arithmetic instructions – to/from the register file • Load/store instructions - to/from memory Memory Processor 1…1100 Register File read/write addr src1 addr src1 data 5 32 32 230 words src2 addr 32 registers ($zero - $ra) 5 dst addr 5 read data src2 data write data 32 32 32 32 bits write data 0…1100 32 32 0…1000 ALU 32 4 5 6 7 0…0100 32 0 1 2 3 0…0000 32 bits byte address (big Endian) word address (binary)

  22. Review: Naming Conventions for Registers 0 $zero constant 0 (Hdware) 1 $at reserved for assembler 2 $v0 expression evaluation & 3 $v1 function results 4 $a0 arguments 5 $a1 6 $a2 7 $a3 8 $t0temporary: caller saves . . . (callee can clobber) 15 $t7 16 $s0 callee saves . . . (caller can clobber) 23 $s7 24 $t8temporary (cont’d) 25 $t9 26 $k0 reserved for OS kernel 27 $k1 28 $gp pointer to global area 29 $sp stack pointer 30 $fp frame pointer 31 $ra return address (Hdware)

  23. Review: Unsigned Binary Representation 231 230 229 . . . 23 22 21 20 bit weight 31 30 29 . . . 3 2 1 0 bit position 1 1 1 . . . 1 1 1 1 bit 1 0 0 0 . . . 0 0 0 0 - 1 232 - 1 232 - 4 232 - 3 232 - 2 232 - 1

  24. 1011 and add a 1 1010 complement all the bits Review: Signed Binary Representation -23 = -(23 - 1) = 23 - 1 =

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