CPT 310 Logic and Computer Design

1. Instructor: David Lubliner Phone 973.596.2878 email : robot1@adm.njit.edu Engineering Technology Dept. Cell 201-960-8018 (important) M-F 10-5PM Text: Logic & Computer Design Fundamentals: 3rd Edition M. Morris Mano & Charles Kime (Software included with text XiLinx version 6.3i) CPT 310Logic and Computer Design Course Summary Detailed Understanding Computer Design Basic Architecture & Logic Pentium 4 • 1 MB L2 Cache • Floating Point Unit • Schedulers • Allocator • Arithmetic & Logic Unit • 16 KB Data Cache • Microcode rom • Trace Cache • Data Translation Buffer • Brach Perdition Unit • Instruction TLB Memory Diagram pg 6 text 10101010 CPU Control Unit Data Path 11011011 Input / Output

2. Grading - CPT 310 • Midterm Exam 25% • Final Exam 25% • Homework 50% • Exercises at the end of chapter • XiLinx Software: schematic editor • Course Summary The object of this course is to provide an understanding of the fundamentals of logic and computer design. The first half covers logic design; number systems, Gates, mapping (Karnaugh maps), arithmetic and sequential circuits and the second half covers digital system design; arithmetic and logic unit (ALU), sequential control design and communication between CPU and i/o devices. The course provides digital system design fundamentals while taking a gradual bottom up development of the fundamentals. • Schedule • Week • 1st 9/7 Course Introduction • 2nd 9/14 Binary numbers/Arithmetic Operations/BCD/Gray codes/ASCII • 3rd 9/21 Combinatorial Logic Circuits Part I / XiLinx Schematic editor Part I • 4th 9/28 Combinatorial Logic Circuits Part 2/ XiLinx Schematic editor Part2 I • 5th 10/5 Combinatorial Logic Design / Hierarch and top down design • 6th 10/12 Combinatorial Functions and Circuits • 7th 10/19 Programmable Logic arrays & devices/Decodes/Multiplexers • 8th Midterm10/26 • 9th 11/2 Arithmetic functions & circuits • 10th 11/9 Sequential circuits • 11th 11/16 Registers and Register Transfers • 12th 11/23 Sequencing & Control Thanksgiving 24th & 25th • 13th 11/30 Computer Design Basics/Instruction set architectures • 14th 12/7 Input-Output and Communications • Reading Days 12/14 • 15th Final 12/21

3. Course Overview Chapter 1: Digital Computers and Information Illustration at beginning of each Chapter Base 10Binary Base 2Octal Base 8 Hex bas 16 08 1000 10 8 15 1111 17 F -Addition -Subtraction BCD Binary Coded Decimal 4 bit code represents number 0-9 Base 10 BCD 0 0000 1 0001 9 1001 Parity Bit (checks for transmission errors Checks if total number of bits is even or odd Number even parity 1000001 01000001 1010100 11010100

4. Course Overview Chapter 2: Combinatorial Logic Circuits Illustration Pg. 32 Logic Circuit Diagrams Clock pulses are used instruct components (gates, etc. to perform the next operation) -Circuit Optimization -2,3,4 level maps 48 elements Optimized to 25 Maps used to optimize circuits Two Var Map Y Y Ex: XY 0 1 0 1 X X 0 1 XY XY 0 1 XY XY 1

5. Xilinx Design & Simulation Software

6. Course Overview Chapter 3: Combinatorial Logic Design Combinatorial Logic Circuit Diagrams Design Hierarchy reduces the complexity required to represent the schematic diagram of a circuit N Inputs M Outputs Combinatorial Circuit Components -Programmable Implementation Devices Represents the function of these circuits

7. Course Overview Chapter 4: Combinatorial Functions and Circuits Sequential Circuit Fundamental circuits decoders, encoders, code converters, multiplexers and programmable logic, which are building blocks for larger circuits and systems. Combinatorial circuit Outputs Inputs Next State Present State Storage Elements CPU Cache Main Memory Decoding An n bit code is capable of representing 2n distinct elements Pg 148

8. Course Overview Chapter 5: Arithmetic Functions and Circuits Iterative Circuit Operates on two n-input input vectors and produces an n-output vector • The concept of iterative circuits made up of arrays of combinatorial cells is introduced. Blocks designed as iterative arrays for performing addition, subtraction and multiplication are covered • Two’s Compliment. ( Subtract by adding ) • Carry Look Ahead Adder ( pg 206 ) 4-bit Ripple Carry Adder Pg 202

9. Course Overview Chapter 6: Sequential Circuits The most basic storage elements are latches, from which flip flops are constructed SR Latch with NOR gates Set-Reset In order to perform useful of flexible sequences of operations we need to be able to construct circuits that can store information betweenoperations. Such circuits are called sequential circuits Synchronous clocked Sequential Circuit J-K Flip-Flop S R Qn+1 1 0 1 0 1 0 0 0 Qn 1 1 Qn S Q Clk Q R Pg 244

10. Course Overview Chapter 7: Registers and Register Transfers 4 Bit Register • Registers are particularly useful for storing information during the processing of data and counters assist in sequencing the processing. • A data path consists of processing logic and a collection of registers that perform data processing. • A control unit is made up of logic that determines the sequence of data processing operations performed by the data path Block Diagram of Registers Pg 316

11. Course Overview Chapter 8: Sequencing and Control Control Unit for Binary Multiplier The focus of this chapter is the control unit. Digital systems can be classified as programmable or non-programmable systems depending on the type of control unit. Non-programmable systems have inputs but do not have any mechanism for executing programs. The focus of this chapter is non-programmable systems, primarily using a multiplier. Programmable systems covered in chapter 10 The control unit determines the operations to be performed and the sequence of those operations based on its inputs and the status bits from the data path. State Table for sequence register and decoder part of multiplier control unit Pg 316

12. Course Overview Chapter 9: Memory Basics Block diagram of 256K by 8 RAM Random access memory (RAM) stores data temporarily. Read only memory (ROM) stores memory permanently. ROM is one form of a variety of components called programmable logic devices (PLDs) that use stored information to define logic circuits There is Internal Cache and external RAM. Decoder: 2 input bits select 1-4 RAM chips Symbol for 64K x 8 RAM chip Pg 412

13. Course Overview Chapter 10: Computer Design Basics Block Diagram of a generic data path The generic data path combined with a control unit and memory forms a programmable system, in this case, a simple computer. An Instruction Set Architecture (ISA) combines control unit, and generic data path are combined to form a CPU (Central Processing Unit). In Programmable units memories are present for storage of data and programs Symbol for n-Bit ALU Arithmetic and Logic Unit Pg 433

14. Discuss Current Architectures