CoGenT: Automatic Co-Generation of Compilers & Simulators for Dynamically Compiled Languages

1. CoGenT: Automatic Co-Generation of Compilers & Simulators for Dynamically Compiled Languages Eliot Moss, presenter Charles Weems and Tim Richards University of Massachusetts Amherst BARC 1/30/03

2. Plan of the talk • Motivation • Generating back-end components • Generating simulator components • Machine description languages • Our approach

3. Motivation • Performance of modern languages • Java as well as C, Fortran • Dynamic compilation, GC, exceptions ... • Explore hardware features • Estimate performance (time, energy, …) Goal: good estimates of performance via simulation

4. We need a simulator that ... • Supports new hardware feature(s) • Has accurate performance measures • Handles language implementation • Dynamic code generation • User-mode signal handlers • Memory mapping, including SEGV

5. AND we need a compiler that ... • Produces code for the (new) target • Does so dynamically • Optimizes competently for the target • Hard if features very novel • Not so bad for ordinary back-end tasks • Instruction selection • Register allocation • Instruction scheduling

6. Need to automate all of this ... • Hard to get simulators right • Especially if you want them fast • Time-consuming to develop them • Can say the same about compilers Point: Generate both, automatically, from machine descriptions

7. Generating back-ends • Prototype framework: Jikes RVM • “Baseline” and optimizing compilers • Instruction selection • Register allocation • Instruction scheduling • Requires simple timing simulator

8. baseline compiler baseline compiler Java bytecode semantics Java bytecode semantics BURS rules BURS rules LIR semantics LIR semantics Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Generating back-end components BURS, Cattell, & Instruction selection Jikes RVM (compiler) Framework Machine descriptions object layout register allocation info Instruction scheduler info simple instruction timing simulator

9. object layout register allocation info Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics Instruction scheduler info simple instruction timing simulator Generating back-end components Register allocation & Instruction scheduling Jikes RVM (compiler) Framework Machine descriptions baseline compiler object layout Java bytecode semantics BURS rules LIR semantics register allocation info Machine Description ISA syntax & semantics Instruction scheduler info simple instruction timing simulator

10. Generating simulator components • Functional simulation • Instruction semantics • Memory contents/function • OS calls • Timing simulation • Pipelines (instruction, FU timing) • Caches, memories, busses, … • Mix and match ISAs, pipelines, etc.

11. Additional simulator components • Instrumentation and tracing • Easy to adjust • Debugging and control

12. functional simulator Machine Description ISA syntax & semantics Generating simulator components Functional simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

13. timing simulator Machine Description ISA syntax & semantics Target pipeline description Generating simulator components Timing simulation semantics support components Machine descriptions Simulator Framework Memory, addressing, program loading, environment, etc functional simulator Java bytecode semantics LIR semantics Cache models, TLB models, memory bus, etc timing simulator Machine Description ISA syntax & semantics debugging support Target pipeline description timing support components

14. Machine description languages and their applications • SLED [Ramsey and Fernández] • λ-RTL [Ramsey and Davidson] • Facile [Schnarr] • MLRISC [George and Leung] • Annotated pipeline graph [Milner] • CCL [Bailey and Davidson] We will assemble the best from these

15. baseline compiler Java bytecode semantics BURS rules LIR semantics Machine Description ISA syntax & semantics functional simulator Java bytecode semantics timing simulator LIR semantics Machine Description ISA syntax & semantics Machine Description ISA syntax & semantics timing simulator Target pipeline description Target pipeline description Instruction scheduler info simple instruction timing simulator The CoGenT prototype Cattell Milner Schnarr SLED,MLRISC,λ-RTL,etc. Simulator Framework Machine descriptions Jikes RVM (compiler) Framework baseline compiler functional simulator Support components object layout Java bytecode semantics BURS rules timing simulator LIR semantics register allocation info Machine Description ISA syntax & semantics debugging support Instruction scheduler info simple instruction timing simulator Target pipeline description