Download
1 / 8
80 likes | 199 Vues
This project in ARM is in part funded by ICT-eMuCo, a European project supported under the Seventh Framework Programme (7FP) for research and technological development. MPSoC 2009. Targeted execution enabling increased power efficiency. John Goodacre Director, Program Management
E N D
This project in ARM is in part funded by ICT-eMuCo, a European project supported under the Seventh Framework Programme (7FP) for research and technological development MPSoC 2009 Targeted execution enabling increased power efficiency John GoodacreDirector, Program Management ARM Processor Division August 2009 Anirban Lahiri Adya Shrotriya Nicolas Zea Technology Researchers
Background • Smooth transition between energy and performance levels • Reduced loss due to leakage power as cores can be switched off • Addresses the application performance diversity Power Big Core Power Aware SMP Scheduled Little Core 1.1 0.8 0.9 1.0 Voltage (V) Fig 1a : Power at Peak performance per Operating Voltage High Performance Applications Power Power Big Core Big Core Tasks Little Core Little Core Tasks Low-power Applications Big-Switch 1000 MIPS 400 700 800 900 100 200 300 1.1 1.2 0.8 0.9 1.0 Voltage (V) Fig 1b : Power-Performance Diversity of Single Task Workloads Fig 1c : Diversity of Multitask Workloads Disclaimer : The plots are indicative of practical architectures and systems.
Analyzing Diversity Core Executing the Task • Code compatibility (due to uniform ISA) ensures easy dynamic task migration (Fig 2a) • Task migration for power efficiency based on required performance (Fig 2b). Example shows a set of tasks T1 – T5 Little Core Big Core Performance (Avg. MIPS) Power (mW) 1000 1000 800 800 Power (mW) MIPS 600 600 400 400 200 200 Time T3 Fig 2a : Single task migrating across cores over time T2 T4 T4 T3 T3 T2 T3 T5 T5 MIPS T1 T5 T4 T1 T2 T1 • Prevents smaller tasks from corrupting high performance task execution. E.g. Task T1 in Fig 2b. • Important to further analyse temporal effects of SoC power Time Fig 2b : Task migrations over time based on performance requirement in a Multitask Workload
Methodologies Being Utilized Flow 1 (High-level Simulation) Flow 3 (Low-level Simulation) Flow 2 (Hardware Emulation) RTL C Code App / OS (Parallel / SMP ?) System Generator Netlist ARMCC / GCC Emulator (Palladium) Simulation (PowerTheater) Statistical Methods Simulator RV Cache Models On-board Execution OS - Profiler Using RVT Cache Hit / Miss Ratio Power per H/w Unit Cache Hit / Miss Ratio OS Behaviour Execution Trace Execution Trace Power Estimation Model Power Estimation Model Power Estimation Model Compare Accuracy
Summary Expectations Possible Power savings up to 50% Performance enhancements up to 30% seen by reducing corruption of high performance tasks Key to still understand the costs of migration
