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Paper Report

Paper Report. A software-based self-test methodology for in-system testing of processor cache tag arrays. G. Theodorou, N. Kranitis, A. Paschalis Department of Informatics & Telecommunications, University of Athens, Greece D. Gizopoulos

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Paper Report

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  1. Paper Report A software-based self-test methodology for in-system testing of processor cache tag arrays G. Theodorou, N. Kranitis, A. Paschalis Department of Informatics & Telecommunications, University of Athens, Greece D. Gizopoulos Department of Informatics, University of Piraeus, Greece On-Line Testing Symposium (IOLTS), 2010 IEEE 16th International Presenter: Jyun-Yan Li

  2. Abstract • Software-Based Self-Test (SBST) has emerged as an effective alternative for processor manufacturing and in-system testing. For small memory arrays that lack BIST circuitry such as cache tag arrays, SBST can be a flexible and low-cost solution for March test application and thus a viable supplement to hardware approaches. • In this paper, a generic SBST program development methodology is proposed for periodic in-system (on-line) testing of L1 dataand instructioncache memory tag arrays (both for direct mappedand set associative organization) based on contemporary March test algorithms. The proposed SBST methodology utilizes existing special performance instructions and performance monitoring mechanisms of modern processors to overcome cache tag testability challenges.

  3. Abstract (cont.) • Experimental results on OpenRISC1200 processor core demonstrate that high test quality of contemporary March test algorithms is preserved while low-cost in-system testing in terms of test duration and test code size is achieved.

  4. What is the Problem • Memory Built-In Self-Test(MBIST) • at-speed and several tests • Impact on chip area and performance • SBST has non-intrusive and flexibility • Defect tag arrays may cause erroneous cache miss • No MBIST circuit because size

  5. Related work Performance counter [16] Direct mapped D$ SBST [14] March compare Detect erroneous cache miss Traditional March [1] March Minimal SS [3] March SS [2] Implement SBST MBIST [5] RAMSES [19] Impact on chip area & performance SBST Memory fault simulator Simulation engine & fault descriptors This paper

  6. Proposal method outline • March SS • Data cache algorithm • Create_address(DB:i:B) • Instruction cache algorithm • Create_address(DB:i:0) TF RDF r0(1): read data (inverted data) B: word offset DB: N-bit word Fetch first instruction in the cache line for alignment

  7. Data cache flow chart M2, M3 ,M4, M5 Load(A) start R hit M0 create address (A) Performance counter =0? Load(A) R hit Yes Prefetch block(A) Prefetch block(A) W tag No W tag No error i=Nd? Test successful Load(A) R hit Yes M1 Prefetch block() create address (A) No K times? W tag No Yes create address () i=Nd? end Yes

  8. Instruction cache flow chart No i=Nd? start create address () Yes M2, M3 ,M4, M5 Enable cache Disable cache Call (A) M0 Performance counter =0? R hit create address (A) Call (A) R hit Disable cache Yes Prefetch block(A) No Prefetch block(A) W tag error Test successful No i=Nd? Enable cache Call (A) Yes No M1 K times? Disable cache create address (A) Yes Prefetch block() end

  9. Experimental result • OpenRISC 1200 • Result: [15] n: total number of bits of the array

  10. Comparison • Write operation • [14]: 6 instructions • This paper: 2 instructions • Read verification • [14]: 7 instructions • This paper: 2 instructions • March C- algorithm

  11. Conclusion • Using March SS algorithm and decreasing code size by performance counter and prefetch instruction • My comment • Assume cache hit to detect cache behaviors by prefetch operation • Some jargons not describe, ex: CF • Fault description’s definition • some March tests do not guarantee complete fault coverage in all fault models

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