1 / 27

ISA I

ISA I. Time Only. CPU = Seconds = Instructions x Cycles x Seconds Time Program Program Instruction Cycle. CPI. “Average cycles per instruction”. CPI ave = (CPU Time * Clock Rate) / Instruction Count = Clock Cycles / Instruction Count. n.

virgil
Télécharger la présentation

ISA I

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. ISA I

  2. Time Only CPU = Seconds = Instructions x Cycles x Seconds Time Program Program Instruction Cycle

  3. CPI “Average cycles per instruction” • CPIave = (CPU Time * Clock Rate) / Instruction Count • = Clock Cycles / Instruction Count n CPU time = ClockCycleTime * CPI * I i i i = 1 n CPI = CPI * F where F = I i i i i i = 1 Instruction Count "instruction frequency" Invest Resources where time is Spent!

  4. MIPS Assembly Language I/O CPU Memory Control Datapath

  5. MIPS Assembly Language • CPU Datapath (extremely simplified) Operation Registers Operand 1 ALU Operand 2 Result

  6. Basic Architecture Model

  7. Software Layer

  8. MIPS Assembly Language Notation

  9. Register (32 bits)

  10. Memory Organization • 32 bits register  8 bits memory • how do byte addresses map onto words? • Can a word be placed on any byte boundary?

  11. 0 1 2 3 Aligned Not Aligned Addressing Objects: Endianess and Alignment • Big Endian: address of most significant byte = word address (xx00 = Big End of word) • IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA • Little Endian: address of least significant byte = word address (xx00 = Little End of word) • Intel 80x86, DEC Vax, DEC Alpha (Windows NT) little endian byte 0 3 2 1 0 lsb msb 0 1 2 3 big endian byte 0 Alignment: require that objects fall on address that is multiple of their size.

  12. Executing an Assembly Instruction

  13. Register File Execution

  14. Register File Execution

  15. Register File Execution

  16. Data Access

  17. Memory Load Operation

  18. Loading data from Memory

  19. Loading data from Memory

  20. MIPS Fields • op – operation to be performed • rs – first source operand • rt – second source operand • rd – register destination operand, gets the result of the operation. • shamt – shift amount – used in shift instructions. • funct – selects specific operation of opcode in op field – R-type……..

  21. MIPS Assembly Language:Instruction Set • 3 different instruction formats • I-type, • R-type, & • J-type (we’ll discuss first two for now)

  22. R-type instructions • R-type • Three register operands • Arithmetic & logical opcodes • Format: • Rd = destination operand (output) • Rs = source operand (input) • Rt = source operand (input)

  23. R-type contd.. Page 90 • R-type: 6 fields • R-type at work • ADD $3,$1,$2 • SUB $7,$4,$5

  24. More R-type examples…… • jr $31 • sltu $3, $8, $9 • mult $5, $6

  25. I-type instructions. • I-type • Two registers and an immediate • Format: • Rt = destination operand • Rs = source operand • Immediate = a constant, also a source operand • Note: immediate operand must fit into 16 bits! (Why?)

  26. !Loads & stores are the data transfer instructions! I-type instructions contd… • I-type: 4 fields • I-type at work • ADDI $2,$1,32 • LUI $7,OxABCD

  27. More I-type examples • lw $5, 60($4) • sw $5, 60($4)

More Related