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IBM Breakthrough: High Speed & Low Power Copper-based SOI Processor 1999. 9. 16 Sungkyunkwan Univ. Jun-Dong Cho h

IBM Breakthrough: High Speed & Low Power Copper-based SOI Processor 1999. 9. 16 Sungkyunkwan Univ. Jun-Dong Cho http://vada.skku.ac.kr. Contents. Why VLSI? Why Low Power? IBM’s Microprocessor Architectures IBM’s Copper Processor: IBM’s Pulsar superscalar RISC IBM’s SOI Technologies

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IBM Breakthrough: High Speed & Low Power Copper-based SOI Processor 1999. 9. 16 Sungkyunkwan Univ. Jun-Dong Cho h

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  1. IBM Breakthrough: High Speed & Low Power Copper-based SOI Processor 1999. 9. 16Sungkyunkwan Univ. Jun-Dong Chohttp://vada.skku.ac.kr

  2. Contents • Why VLSI? Why Low Power? • IBM’s Microprocessor Architectures • IBM’s Copper Processor: IBM’s Pulsar superscalar RISC • IBM’s SOI Technologies • IBM’s Future Enhancements

  3. Why VLSI? Moore’s Law • Gordon Moore: co-founder of Intel. • Predicted that number of transistors per chip would double every 18 months. • Integration improves the design: • lower parasitics = higher speed • lower power • physically smaller • reduces manufacturing cost

  4. Silicon in 2010 Die Area: 2.5x2.5 cm Voltage: 0.6 V Technology: 0.07 m

  5. Portable systems long battery life light weight small form factor IC priority list power dissipation cost performance Technology direction reduced voltage/power designs based on mature high performance IC technology, high integration to minimize size, cost, power, and speed Why Lower Power

  6. Low Power MPU

  7. Power(W) Alpha 21164 Alpha 21264 50 P III 500 45 P II 300 40 35 Alpha21064 200 30 25 P6 166 20 P5 66 15 P-PC604 133 10 i486 DX2 66 P-PC601 50 i486 DX25 5 i386 DX 16 i486 DX4 100 i286 i486 DX 50 P-PC750 400 1980 1985 1990 1995 2000 year Microprocessor Power Dissipation

  8. IBM’s Multi-Chip Modules

  9. VON NEUMANN vs HARVARD

  10. IBM’s PowerPC Lower Power Architecture • Optimum Supply Voltage through Hardware Parallel, Pipelining ,Parallel instruction execution • 603e executes five instruction in parallel (IU, FPU, BPU, LSU, SRU) • FPU is pipelined so a multiply-add instruction can be issued every clock cycle • Low power 3.3-volt design • Use small complex instruction with smaller instruction length • IBM’s PowerPC 603e is RISC • Superscalar: CPI < 1 • 603e issues as many as three instructions per cycle • Low Power Management • 603e provides four software controllable power-saving modes. • IBM’s Blue Logic ASIC :New design reduces of power by a factor of 10 times

  11. New Generation 64-bit PowerPC • IBM’s Pulsar superscalar RISC microprocessor uses an innovative copper technologies with 1.8 volts power supply. • The lower power supply voltage coupled with the smaller circuit dimensions results in 22 watts of maximum power at 450MHz for Pulsar compared to NorthStar’s 27 watts at 262 MHz.

  12. Power PC (64 bit RISC)

  13. Power-Down Techniques Lowering the voltage along with the clock actually alters the energy-per-operation of the microprocessor, reducing the energy required to perform a fixed amount of work

  14. Voltage vs Delay • Use Variable Voltage Scaling or Scheduling for Real-time Processing • Use architecture optimization to compensate for slower operation, e.g., Parallel Processing and Pipelining for concurrent increasing and critical path reducing.

  15. Low Voltage Main Memories

  16. Power PC Low Power Management • Baseline: use right supply and right frequency to each part of the system. • Four power-saving modes: • Full on mode for full speed • Doze mode in which the execution units are not running • Nap mode which also stops the bus clocking • Sleep mode which also stops the clock generator (20-100mW saving). • Dynamic Management mode: enter a low power mode when the functional units are idle.

  17. PowerPC Dynamic Power Management

  18. RS/6000 SP • RISC-based microprocessor:PowerPC604e • Up to 128 processor nodes (512:special order) • Up to 160 gigabytes of memory, 2.5 terabytes of disk space. • A peak speed of 204 gigaflops • Application, reliability, availability, and price/performance

  19. RS/6000 SP: Configuration Flexibility • Deliver the processing power required for large and complex applications • Allow the flexibility to configure for optimum commercial or technical computing application performance. • Three sizes of RISC nodes (thin, wide, and high) mixed in a computing system (up to 128 node, 512 by special order). • Supports many communication protocol, adapters, and peripherals for a flexible system

  20. IBM’s Aggressive Work • Copper Process: the biggest advances in integrated circuits since they were invented 35 years ago. • IBM T.J. Watson at Yorktown Heights, NY (Semiconductor Research & Development Center) • It shows that IBM is still a technological leader.. People may have forgotten that IBM has this other value, that they have an R&D lab that is really cutting edge, and I think that is important. - E. Rosenfeld, Stock analyst, on CNBC, Sep. ‘97

  21. Why Copper Processor? • Motivation: Aluminum resists the flow of electricity as wires are made thinner and narrower. • Performance: 40% speed-up • Cost: 30% less expensive • Power: Less power from batteries • Chip Size: 60% smaller than Aluminum chip

  22. Copper Processor • Six levels of copper

  23. A new PowerPC(Sep. 98): 34 million transistors, 0.22-micron copper CMOS tech, with six levels of copper interconnect. 2-issue (two 32-byte data read at a time) 128KB on-chip L1 instruction cache 218KB on-chip L1 data cache with one cycle latency On-Chip L2 cache directory with 8 MB off-chip L2 cache 14.4 Giga Byte/s L2 cache bandwidth 23 byte wide on-chip busses 450 MHz operating frequency 140 mm2 die size 22 watts maximum power (1.8 volts) 4 way superscalar 5 stage deep pipeline World’s First Copper-based MicroProcessor:PowerPC740/750

  24. Silicon-on-Insulator • How Does SOI Reduce Capacitance ? • Eliminated junction capacitance by using SOI (similar to glass) is placed between the impuritis and the silicon substrate

  25. Why Silicon-on-Insulator • Performance Low Power Soft Error Rate

  26. Next Generation • SOI (Silicon On Insulator) and Copper Process enables to shrink channel lengths to 0.12-micron and further reduction in capacitance and resistance. • Speed-up from 540 MHz up to 675 MHz • IBM is contracting Compaq to leverage IBM’s SOI and copper process to produce 1GHz Alphas ahead of Samsung

  27. References • J.M.Borkenhagen, S. Storino, Commercial Microprocessor Design, IBM Server Group Development, Rochestor, Minnesota • D. Allen, et. Al., A 0.2-micron 1.8V SOI 550 MHz 64b PowerPC Microprocessor with Copper Interconnects, IEEE ISSCC99. • Http://www.chips.ibm.com/

  28. Conclusion • IBM’s Leading-Edge HS & LP Microprocessor Architectures • World-First Copper Processor: IBM’s Pulsar superscalar RISC • IBM’s MCM and SOI Technologies

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