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Synchronization of complex systems

Synchronization of complex systems. Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain. Thanks to A. Chakraborty, T. Chelcea, M. Greenstreet and S. Nowick. Multiple clock domains. CLK1. f1/f0. CLK (f0). f2/f0. CLK2. CLK0. CLK. f3/f0. CLK3. Independent clocks

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Synchronization of complex systems

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  1. Synchronization ofcomplex systems Jordi Cortadella Universitat Politecnica de Catalunya Barcelona, Spain Thanks to A. Chakraborty, T. Chelcea,M. Greenstreet and S. Nowick

  2. Multiple clock domains CLK1 f1/f0 CLK (f0) f2/f0 CLK2 CLK0 CLK f3/f0 CLK3 Independent clocks (plesiochronousif frequenciesclosely match) Single clock (Mesochronous) Rational clock frequencies

  3. The problem: metastability D Q D Q ФT ФR ФR setup hold D Q ?

  4. D D D D Q Q Q Q Classical “synchronous” solution ФT ФR Example Mean Time Between Failures fФ: frequency of the clock fD: frequency of the data tr: resolve time available W: metastability window : resolve time constant

  5. How to live with metastability ? • Metastability cannot be avoided, it must be tolerated. • Having a decent MTBF ( years) may result in atangible impact in latency • Purely asynchronous systems can be designedfailure-free • Synchronous and mixed synchronous-asynchronous systems need mechanisms with impact in latency • But latency can be hidden in many cases …

  6. Different approaches • Pausible Clocks (Yun & Donohue 1996) • Predict metastability-free transmission windows for domains with related clocks (Chakraborty & Greenstreet 2003) • Use the waiting time in FIFOs to resolve metastability(Chelcea & Nowick 2001) • And others … • The term “Globally Asynchronous, Locally Synchronous” is typically used for these systems (Chapiro 1984)

  7. Mutual exclusion element 0 ack1 req1 1 0 req2 1 0 ack2 0

  8. Metastability

  9. Mutual exclusion element Metastability resolver 0 1 0 ack2 req1 req2 ack1 1 0 0 An asynchronous data latch with MS resolver can be built similarly

  10. Abstraction of the MUTEX R1 G1 MUTEX R2 G2

  11. Environment MUTEX [δ1, δ2] delay A pausible clock generator

  12. Cntr delay Pausible clocks Req Ack FF ME MUTEX [δ1, δ2] CLK Yun & Dooply, IEEE Trans. VLSI, Dec. 1999 Moore et al., ASYNC 2002

  13. STARI (Self-Timed At Receiver’s Input) • Both clocks are generated from the same source • The FIFO compensates for skew between transmitter and receiver • M. Greenstreet, 1993

  14. A Minimalist Interface • FIFO reduces to latch-X and a latch controller • Φx can always be generated in such a way as to reliably transfer data from input to output • Chakraborty & Greenstreet, 2002

  15. A Minimalist Interface: 3 scenarios Latch-X setup & hold Latch-R setup & hold Фx Permitted The scenario is chosenat initialization

  16. A Minimalist Interface: latch controller The controller detects which transition arrives first (from ΦT and ΦR) and generates ΦX accordingly

  17. A Minimalist Interface: rational clocks

  18. A Minimalist Interface: arbitrary clocks • Assumption: clocks are stable • Each domain estimates the other’s frequency • Residual error corrected using stuff bits

  19. Asynchronous Domain Synchronous Domain 2 Synchronous Domain 1 Mixed-Timing Interfaces Async-Sync FIFO Async-Sync FIFO Sync-Async FIFO Mixed-Clock FIFO’s Chelcea & Nowick, 2001

  20. Mixed-Clock FIFO: Block Level full req_get valid_get req_put synchronous get interface Mixed-Clock FIFO synchronous put inteface empty data_put data_get CLK_put CLK_get

  21. Controls get operations Mixed-Clock FIFO: Block Level Initiates put operations Initiates get operations Bus for data items Bus for data items full req_get valid_get req_put synchronous get interface Mixed-Clock FIFO synchronous put inteface empty data_put data_get CLK_put CLK_get Controls put operations

  22. Mixed-Clock FIFO: Block Level Indicates data items validity (always 1 in this design) Indicates when FIFO full full req_get valid_get req_put synchronous get interface Mixed-Clock FIFO synchronous put inteface empty data_put data_get CLK_put CLK_get Indicates when FIFO empty

  23. cell cell cell cell cell Mixed-Clock FIFO: Architecture full Full Detector req_put Put Controller data_put CLK_put CLK_get data_get req_get valid_get Get Controller Empty Detector empty

  24. En SR En Mixed-Clock FIFO: Cell Implementation CLK_put en_put req_put data_put ptok_out ptok_in f_i REG e_i gtok_out gtok_in CLK_get en_get valid data_get

  25. En SR En Mixed-Clock FIFO: Cell Implementation CLK_put req_put en_put data_put ptok_out ptok_in PUT INTERFACE f_i REG e_i GET INTERFACE gtok_out gtok_in data_get CLK_get en_get valid

  26. Synchronization: summary • Resolving metastability implies latency • Latency can be often hidden (FIFOs, Chelcea & Nowick) • Clock frequencies can be estimated and clock edges predicted under the assumption of stable clocks (Chakraborty & Greenstreet) • Pausible clocks are also possible (Yun & Donohue 1996) • But still the nicest solutions are totally asynchronous • As presented by Fulcrum Microsystems in the last lecture

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