Bill Eklow October 26, 2011 3D Test Issues
3D Test Challenges – Key Areas (http://www.itrs.net/) • Defects • TSV’s • Test access • Test Flows/Test Scheduling • Heterogeneous Die • Debug • Power
3D Sources of defects (known good -> unknown) • Thermal (Reliability, Performance) • Mechanical (stress induced timing variations) • Contamination (signal integrity, performance) • Fabrication/Assembly process (wafer thinning, stacking, TSV insertion) • http://wiki.sematech.org/Reliability-Elements
Industry is looking at the red circles (easy problems) – needs to look at the green circles (hard problems) TSV Testing – Defect/Fault Models
TSV Voids Should be easy to detect this void
Subtle TSV Voids Can we detect this void?
3D Access Best case currently is probing 35 um target diameter Need to probe here to test TSV integrity
TSV Testing Assumptions • Static (stuck-at) testing insufficient • Defect isolation (die vs stack) • Physical access to TSVs is doubtful (5 m diameter, 10 m pitch) • Physical access to -bumps is questionable (25 m diameter, 40 m pitch)
TSV Testing – Possible Solutions • High speed, die-level test wrappers • Die-level, interposer-level TSV monitors/BIST • EDA solution (full stack ATPG, MemBIST) • Serdes based BIST solutions for very high speed signals
Test Access • Access to on die DFX features • Capability to bypass the die • Capability to route to the next die • Capability to “terminate”/turnaround data • Self-assembling • Physical aspect (P1838) • Logical aspect (1149.1/1500 based) • Wide I/O access impractical for non-memory stacks • Key is integrating “off the shelf” die with custom die/stack (may require “test interposers”) • Stack level test controller • Advances needed in: probing, cleaning, metallurgies
3D Stack Yields For homogenous structures, the yield (y) is given by y = YN, where Y = chip yield and N = number of chips in the stack.1 For example, if we stack up 8 homogenous chips (N=8) and the chip yield Y=80%, then the 3D chip-stack yield = 17%. However, if the chip yield is increased from 80 to 99%, the 3D chip-stack yield increases dramatically to 92%. Of course, for KGD (Y=100%), the 3D chip-stack yield is 100% (assuming the assembly yield is 100% and the test detects all the possible faults whenever they are present). It can be seen that “good” or “high” chip yield is very important for 3D integration. For heterogeneous structures, the 3D integration yield (y) is given by y = (XR)(YS)(ZT)…, where X, Y, Z… = chip yield for different chip type and R, S, T… = number of different types of chips.2For example, if we stack up a wide I/O DRAM, which consists of one logic and four DRAMs and their respective chip yields are 66% and 68%. The wide I/O DRAM stack yield (y) is y = (.66)1(.68)4 = is 21%. When the chips are mature, e.g., the chip yield for the logic is 90% and the DRAM is 95%, then the yield of the wide I/O DRAM is y = (.90)(.95)4 =73%.
Test Flow Challenges • Key assumption: Mid-bond testing impractical in most cases • Test flow modeling includes: test time, tester resources/test data volume, yield, cost • KGD -> PGD -> NSGD (requires significant DFM&Y) • Mid-bond testing may be required due to cost-weighted yield (includes test insertion costs) • Greater reliance on functional tests (die to die interactions) • Test scheduling for parallel testing • What about burn-in? Who pays for yield loss? • Adaptive test/traceability introduces: data storage/transfer/security issues
Debug/FA • Key assumption: • Mid-bond testing impractical in most cases • Stack disassembly impractical in nearly all cases • Design for Debug is as important as Design For Test • Monitors and Data Capture will comprise a significant % of test logic • Speed • Droop • SI • Thermal • Die to Die defect isolation will be very difficult • Recreating failure mechanism at die supplier will be nearly impossible and very costly
DFT for 3D • Boundary-scan based access (may need to be augmented by high speed test) • Built-in test features to enable die level testing at ATE and in stack (validate xGD) • Die level wrappers to facilitate TSV testing and some die to die testing • Test monitors for fault isolation • Fault tolerance/redundancy • Tester in the stack (test interposer) • Future DFT based on learnings from assembly process