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3D Test

Alfred L. Crouch ASSET, Austin, TX Chief Technologist & Director of IJTAG R&D Vice-Chair IEEE P1687 “IJTAG” Working Group Member IEEE 3D Study Group acrouch@asset-intertech.com. 3D Test. What is 3D Test and Why is it Different?. Day One of the Study Group…. 1. Saman Adham

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3D Test

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  1. Alfred L. Crouch ASSET, Austin, TX Chief Technologist & Director of IJTAG R&D Vice-Chair IEEE P1687 “IJTAG” Working Group Member IEEE 3D Study Group acrouch@asset-intertech.com 3D Test What is 3D Test and Why is it Different?

  2. Day One of the Study Group… 1. Saman Adham 2. Lorena Anghel 3. Patrick Y Au 4. Paolo Bernardi 5. Sandeep Bhatia 6. Vivek Chickermane 7. Eric Cormack 8. Adam Cron 9. Al Crouch 10. Shinichi Domae 11. Ted Eaton 12. Bill Eklow 13. Jan Olaf Gaudestad 14. Michelangelo Grosso 15. Said Hamdioui 16. Michael Higgins 17. Gert Jervan 18. Hongshin Jun 19. Rohit Kapur 20. Santosh J Kulkarni 21. Philippe Lebourg 22. StephaneLecomte 23. Hans Manhaeve 24. Erik Jan Marinissen 25. Teresa McLaurin 26. Ken Parker 27. Herb Reiter 28. Mike Ricchetti 29. Andrew Richardson 30. Daniel Rishavy 31. JochenRivoir 32. Volker Schober 33. Eric Strid 34. Thomas Thaerigen 35. IoannisVovlatzis 36. Min-Jer Wang 37. Lee Whetsel BTW 2010

  3. The 3D Study Group Goal • To investigate whether an IEEE Standard is needed to cover 3D chips – and to generate a PAR if the answer is yes… • …not everyone on the committee understands this and some are trying to solve the problem… • 5.2 Scope of Proposed Standard: The proposed standard is a ‘die-centric’ standard; it applies to a die that is pre-destined to be part of a multi-die stack and such a die can be compliant (or not compliant) to the standard. The proposed standard defines die-level features, that, when compliant dies are brought together in a stack, comprise a stack-level architecture that enables transportation of control and data signals for the test of (1) intra-die circuitry and (2) inter-die interconnects in both (a) pre-stacking and (b) post-stacking situations, the latter for both partial and complete stacks, in both pre-packaging and post-packaging situations. The primary focus of inter-die interconnect technologies addressed by this standard is Through-Silicon Vias (TSVs); however, this does not preclude its use with other interconnect technologies such as wire-bonding. • The standard will consist of two related items. • 1. 3D Test Wrapper On-die hardware features that enable transportation of test (control and data) signals in the following configurations. • • Pre-stacking: From on-die I/Os to die-internal DfT features, and vice versa. • • Post-stacking • ‘Turn’ mode: From on-die I/Os to die-internal DfT features, and vice versa. These on-die I/Os might be external I/Os and/or inter-die interconnections coming from (or going to) an adjacent die. • ‘Elevator’ mode: From on-die I/Os, through THIS DIE, to the inter-die interconnections to an adjacent die, and vice versa. These on-die I/Os might be external I/Os and/or inter-die interconnections coming from (or going to) another adjacent die. • 2. Description A description of the Test Wrapper features in a standardized human- and computer-readable language. This description should allow the usage of the die within a multi-die stack for test and test access purposes. BTW 2010

  4. What does this mean? • Human POV: We want to treat individual die like “Lego Blocks” • The Board-to-Chip is the Big Green thing • The Chip-to-Chip are the bumps and holes • The PAR is to create the Working Group to investigate: • the JTAG-like connection to the Big Green thing… • Is it 1149.1, is it 1149.7, is it other? Do we stipulate this, or assume it • …and to define the per-die connection for test/debug on each die • Physical Vias/Locations, Pin/Signal Protocol, Number of, etc. • …and the support and interaction for existing and proposed IEEE Standards such as 1149.1, 1149.6, 1500, P1687 • Incorporate the existing, create and add the new BTW 2010

  5. What’s the Problem - in Words? • Bare “first-floor” die must be tested and must become a KGD • Must be able to be manufactured, tested and delivered before stacking or final packaging • Must be able to be stacked (W-on-W, D-on-D, D-on-W) • Must be able to be tested after stacking – partial, total, final • May need to be tested-debugged after packaging (IC failure-analysis, board test, system test, field returns) • Bare “upper-story” die must be tested and must become a KGD • Must be able to be manufactured, tested and delivered before stacking or final packaging • Must support Probe Pads • Must be able to be stacked (W-on-W, D-on-D, D-on-W) • Must be able to be tested after stacking – partial, total, final • May need to be tested-debugged after packaging (IC failure-analysis, board test, system test, field returns) • Whole Stack may have requirements different than single IC or planar-MCM • There may be new defect/fault models such as thermal hot spots or die-to-die noise interference • There may be a need to test individual die or to access items on individual die without involving other die or other items (test/debug in isolation) • There may be die-to-die tests such as interconnect or unit-to-unit operations BTW 2010

  6. Distribution of IEEE Standard Solution Spaces 1500+ Chip-Level 1149.7 IF 1149.1 IF 1687 IF 1500 IF Instrument Explanation: If there is no 1149.7, thenthere may be a chip-level1149.1 TAP and TAPC;or there may be more thanone TAP and TAPC; orthere may be one TAPbut multiple TAPCs usingCompliance Enable pinsto select the active TAPC. SGB (TDR) Explanation: 4 Standards exist to access“inside the chip” logic called Cores and Instruments Each Standard has apurpose and an application section. The 1149.7 sectionconcerns access to manyTAPs through packets ofdata and control and maybea reduced pin interface. The dot-7 may be at theboard and/or on the chip. Explanation: The TAPC should connectto a Standard IF using 1Instruction – furtheractions are all ScanDRs 1687 can be anembedded TDR or can bean optional hierarchicalconnection TDR 1687 TDR WIR WBR CDR SIB Instrument MultipleTAPCs TAP.1 Instrument 1687 TDR Explanation: 1500 has TDRs arrangedin parallel and requires aMux Select in addition toan 1149.1 interface – madefor Embedded Core access AltTAPC TAP.1 Described by CTL Dynamic ScanChains Described by HSDL/BSDL Described by BSDL TAPC.7 BScanTAPC SIB Described by ICL/PDL TAP.7 TAP.1 5

  7. Distribution of IEEE Standard Solution Spaces 1500+ Chip-Level 1149.7 IF 1149.1 IF 1687 IF 1500 IF Instrument SGB (TDR) 1687 TDR WIR WBR CDR SIB Instrument MultipleTAPCs TAP.1 Instrument 1687 TDR AltTAPC TAP.1 Described by HSDL/BSDL Described by BSDL TAPC.7 BScanTAPC SIB Described by ICL/PDL Described by CTL TAP.7 TAP.1 …by ICL/PDL 6

  8. What’s the Problem – in Pictures? • Bottom or Base Diecan be Tested to • become a (KGD)Known-Good-Die • Want high coverage • No Test Escapes • Must have Probe Pads • Must have a TAP • TAP-1 or TAP-7 • 1149.1 B-Scan for I/O • must have access to: • Core Test • Embedded Test • Embedded Debug • must have TSVs to: • access upper die CPU Core DSP Core Mem Core 1687 1687 Scan &Debug Scan &Debug LBIST MBIST TestTSV 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Logic TCK TMS TDI TDO 1149.1 TAP & Ctrl TempMon Scan 1500 Wrapper 1149.7 Interface 1149.1 Logic 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl FLASH Core Boundary Scan High Speed IO Other Wrapper MBIST 1687 1687 Other Wrapper?

  9. What’s the Problem – in Pictures? • Each “Upper” Die must have: • Known-Good-Die Test • Stack Test • Must have a few Probe Padsfor bare-die test or partialstack test • May use 1500 WBR or1149.1 BSR forInterconnect Test • Prefer P1687 SIB formanagement of ScanPath lengths and Instrument Scheduling CPU Core DSP Core Mem Core 1687 1687 Scan &Debug Scan &Debug LBIST MBIST 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core TCKC 1687 TempMon TMSC Scan 1149.7 Logic 1149/1500 BSR/WBR 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl FLASH Core 1687 1687 • Dot-7 I/O on each Die has2 TSVs to feed Stacked-Die • TMSC • TCKC MBIST

  10. Some Various Access Proposals • The “1149.7 Multiple-TAP Access” Proposal • The “1149.1 TAP on Base-Die Only” Proposal • The “1149.1 Prime TAP on each Die” Proposal • The “1149.7 to Prime TAP on each Die” Proposal

  11. The 1149.7 Multiple TAP Proposal • There is an 1149.7 TAP on the Base Die which becomes a two-wire distribution network to all the TAPs one each die • There are two-TSVs on each die to deliver these signals (three-signals and three-TSVs if a Mux is used instead of a bidirectional TDI-TDO function) • There are 1149.1 TAPs associated with groups of logic or cores – and there is an 1149.7 Controller in front of each 1149.1 TAP • This method places more logic on each die (multiple dot-1 and dot-7 TAPs, multiple core-wrappers), but makes each addressable item a self-contained and locally controlled unit with 1149.7 only being a data/control delivery conduit – not a controller source for configuration or instructions.

  12. An Access Solution: “1149.7 Multiple-TAP Access” • Bottom Die • Known-Good-Die • Must have Probe Pads • Must have a TAP • TAP-1 or TAP-7 • Speed to Instrument • 1149.1 Boundary Scanfor I/O CPU Core DSP Core Mem Core 1687 1687 Scan &Debug Scan &Debug LBIST MBIST 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core TCKC TMSC 1687 TempMon Scan • Dot-7 has twoTSVs to feedStacked-Die • TMSC • TCKC 1149.7 Logic 1149.7 Interface 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.7 Interface 1149.1 Logic 1149.1 TAP & Ctrl 1149.7 Interface 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl FLASH Core MBIST 1687 1687 • My Preference • More on-chip Logic • but Self-Containedand Scalable

  13. An Access Solution: “1149.7 Multiple-TAP Access” • Die 2-up-to-Die N • Known-Good-Die Test • Stack Test • Must have a fewProbe Pads (Mux or SIB)for KGD • May use 1500 WBR or1149.1 BSR forInterconnect Test • Prefer P1687 SIB formanagement of ScanPath lengths and Instrument Scheduling CPU Core DSP Core Mem Core 1687 1687 Scan &Debug Scan &Debug LBIST MBIST 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core TCKC 1687 TempMon TMSC Scan 1149.7 Logic 1149/1500 BSR/WBR 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl • Dot-7 I/O on each Die has2 TSVs to feed Stacked-Die • TMSC • TCKC FLASH Core 1687 1687 MBIST Issue: each grouping adds aTAP and a Wrapper (Logic) Note: many die already havemultiple TAPs and could extend easily

  14. An Access Solution: “1149.7 Multiple-TAP Access” CPU Core CPU Core DSP Core DSP Core Mem Core Mem Core 1687 1687 1687 1687 Scan &Debug Scan &Debug Scan &Debug Scan &Debug LBIST LBIST MBIST MBIST TCKC 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core ASIC Core TCKC 1687 TempMon TMSC TMSC 1687 TempMon Base Diewith Pins Scan Scan Stacked Diewith only Vias 1149.7 Logic 1149/1500 BSR/WBR 1149.7 Logic 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.7 Interface 1149.1 TAP & Ctrl 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.7 Interface 1149.1 Logic 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.7 Interface 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.1 TAP & Ctrl 1149.7 Interface 1149.1 TAP & Ctrl FLASH Core FLASH Core 1687 1687 MBIST MBIST There are 2 physical Vias The connection is broadcast-Star There is more logic to define address and extract packet data There are probe pads on upper die There is a 1500 or 1149.1 type boundary scan for TSVs between die 1687 1687 BTW 2010

  15. The 1149.1 TAP on Base-Die Only Proposal • There is one 1149.1 TAP on the Base Die which becomes a controller for all die in the stack – it provides the control signals for all JTAG-compliant object in the entire die stack • There are up to seven-TSVs on each die to deliver these signals control and data signals • ShiftEn • CaptureEn • UpdateEn • TCK • TDI • TDO (single TDO requires a Multiplexor and a Select on each die) • ResetN (opt) • There are 1500 Wrappers/1687 Registers associated with groups of logic or cores – and they use these 1149.1 signals to coordinate all operations • This method places the entire brunt of signal loading and instruction delivery on the single TAP Controller on the Base-Die – even if the die and number of die to eventually be placed above the base-die are unknown at the time of design; there is also a TDO management issue if only one TDO-TSV is used

  16. An Access Solution: “1149.1 TAP on Base-Die Only” CPU Core CPU Core DSP Core DSP Core Mem Core Mem Core Scan &Debug Scan &Debug Scan &Debug Scan &Debug 1687 1687 1687 1687 LBIST LBIST MBIST MBIST SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core ASIC Logic S 1149.1 Logic SIB C U Scan Scan Tck 1687 1687 TempMon TempMon Tdi SIB Tdo R FLASH Core FLASH Core SIB There are 7 physical Vias – issue, unknown loading on base die instruction-register The connection is serial-daisy-chain with SIB for turn-around There is more routing to create access and control The 1687 SIB or a 1500 Mux structure can be used for bypass and turn-around There are probe pads on upper die There is a 1500 or 1149.1 type boundary scan for TSVs between die MBIST MBIST 1687 1687 1687 1687 SIB BTW 2010

  17. SC U The Segment-Insertion-Bit (SIB) The Key Element for Adding, Organizing, Managing Embedded Content TDO Shift-Update Cellused as a SIB NormalTDI-TDOScan Path DefaultConfigurationfrom Reset fromScanOut toScanIn Select TDI 0 The HIP TCK Scan Path Management Bit

  18. SC U The Segment-Insertion-Bit (SIB) The Key Element for Adding, Organizing, Managing Embedded Content TDO Shift-Update Cellused as a SIB AddedNetworkScan Path Can accessother SIBsor InstrumentInterface TDR fromScanOut toScanIn Select TDI 1 The HIP TCK Scan Path Management Bit

  19. SC U The Network-Instruction-Bit (NIB) The Key Element for Local Configuration of Scan Path Networks Shift-Update Cellused as a NIB TDO Can accessother SIBsor InstrumentInterface TDRs Network Command TDI 1 TCK Scan Path Network Command Bit

  20. An Access Solution: “1149.1 TAP on Base-Die Only” • Bottom Die • Known-Good-Die • Must have Probe Pads • Must have a TAP • TAP-1 or TAP-7 • Speed to Instrument • 1149.1 Boundary Scanfor I/O Issue – unknown loading on instructions/signals CPU Core DSP Core Mem Core Scan &Debug Scan &Debug 1687 1687 LBIST MBIST SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core TMS TCKTDI TDO 1149.1 Logic SIB • Dot-1 on 1st floor-onlyhas seven TSVs tofeed Stacked-Die • ShiftEn • CaptureEn • UpdateEn • TCK • TDI • TDO • ResetN (opt) Scan 1687 TempMon SIB FLASH Core SIB MBIST 1687 1687 SIB Note: 3 potential TDOarchitectures – Mux,Daisy-Chain, SIB

  21. The 1149.1 Prime TAP on Each Die Proposal • There is one 1149.1 TAP on Each Die which becomes a controller for all JTAG-Compatible functions on each die – it locally provides the control signals for all JTAG-compliant objects in each die • There are up to five-TSVs on each die to deliver the 1149.1 TAP signals • TMS • TCK • TDI • TDO (TDO managed to one pin on each die) • TRST* (optional) • Each die is a complete system similar to testing an MCM or chips on a board • This method creates an Instruction Compatibility Issue in that parallel operation of each TAP implies parallel (Identical) operation of each TAP Controller (identical data and instruction flows into each dies TDI) – unless each die’s TDI-TDO is daisy chained

  22. An Access Solution: “1149.1 Prime TAP on each Die” CPU Core CPU Core DSP Core DSP Core Mem Core Mem Core Scan &Debug Scan &Debug Scan &Debug Scan &Debug 1687 1687 1687 1687 LBIST LBIST MBIST MBIST SIB SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Logic ASIC Core 1149.1 TAPC 1149.1 TAPC SIB SIB Scan Scan 1687 1687 TempMon TempMon SIB SIB FLASH Core FLASH Core SIB SIB There are 7 physical Vias – each die has its own TAP that operates simultaneously (star) The internal die connection is serial-daisy-chain with SIB for turn-around There is more routing to create access and control The 1687 SIB or a 1500 Mux structure can be used for bypass and turn-around There are probe pads on upper die There is a 1500 or 1149.1 type boundary scan for TSVs between die MBIST MBIST 1149.1 BSR or1500WBR 1687 1687 1687 1687 SIB SIB BTW 2010

  23. An Access Solution: “1149.1 Prime TAP on each Die” • Die 2-to-N • Known-Good-Die • Stack Test • Must have a fewProbe Pads (Mux or SIB)for KGD • May use 1500 WBR or1149.1 BSR forInterconnect Test • Prefer P1687 SIB formanagement of ScanPath lengths and Instrument Scheduling CPU Core DSP Core Mem Core Scan &Debug Scan &Debug 1687 1687 LBIST MBIST SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Logic 1149.1 TAPC SIB TMS TCK TDI TDO TRST* Scan 1687 TempMon SIB FLASH Core • Dot-1 I/O on eachDie has 4/5 TSVs tofeed Stacked-Die • TMS, TCK, TDI, TDO • TRST* SIB MBIST 1149.1 BSR or1500WBR 1687 1687 • Issues: 1149.1 TAPCInstruction Overlap • TAPs operate in parallel • Must have CE TSV per Die SIB

  24. The 1149.7 to Prime TAP on Each Die Proposal • There is one 1149.1 TAP on Each Die which becomes a controller for all JTAG-Compatible functions on each die – it locally provides the control signals for all JTAG-compliant objects in each die • There are two-TSVs on each die to deliver the 1149.7 TAP signals • TMSC • TCKC • The two-TSVs feed the one Prime TAP on each Die • Each die is a complete system similar to testing an MCM or chips on a board • This method solves the Instruction Compatibility Issue the previous method in that each TAP only processes the packets targeted to its 1149.7 address

  25. An Access Solution: “1149.7 to Prime TAP per Die” CPU Core CPU Core DSP Core DSP Core Mem Core Mem Core Scan &Debug Scan &Debug Scan &Debug Scan &Debug 1687 1687 1687 1687 LBIST LBIST MBIST MBIST SIB SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Core ASIC Logic 1149.7 TAPC 1149.7 TAPC 1149.1 TAPC 1149.1 TAPC SIB SIB Scan Scan 1687 1687 TempMon TempMon SIB SIB FLASH Core FLASH Core SIB SIB There are 2 physical Vias – each die has its own TAP that operates simultaneously and thoseTAPs are addressed by 1149.7 2-wire interface The internal die connection is serial-daisy-chain with SIB for turn-around There is more routing to create access and control The 1687 SIB or a 1500 Mux structure can be used for bypass and turn-around There are probe pads on upper die There is a 1500 or 1149.1 type boundary scan for TSVs between die MBIST MBIST 1149.1 BSR or1500WBR 1687 1687 1687 1687 SIB SIB

  26. An Access Solution: “1149.7 to Prime TAP per Die” • Die 2-to-N • Known-Good-Die • Stack Test • Must have a fewProbe Pads (Mux or SIB)for KGD • May use 1500 WBR or1149.1 BSR forInterconnect Test • Prefer P1687 SIB formanagement of ScanPath lengths and Instrument Scheduling CPU Core DSP Core Mem Core Scan &Debug Scan &Debug 1687 1687 LBIST MBIST SIB 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper 1500 Wrapper ASIC Logic 1149.7 TAPC 1149.1 TAPC SIB TMSC TCKC Scan 1687 TempMon SIB FLASH Core • Dot-1 I/O on eachDie has 4/5 TSVs tofeed Stacked-Die • TMS, TCK, TDI, TDO • TRST* SIB MBIST 1149.1 BSR or1500WBR 1687 1687 SIB My 2nd Preference

  27. Summary-Conclusions • An IEEE effort has been started with a Study Group • The Study Group is currently finishing up a PAR to create a Working Group • There are a number of potential architectures that have been investigated to help define the elements of the work to be done • The effort will include definition of an architecture, a description language, and maybe a vector relationship • Architecture tradeoffs will include number of TSVs, location of TSVs, impact of logic/routing/power, and maybe required structures, and access efficiencies BTW 2010

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