1 / 17

Sandeep Pande and Fearghal Morgan Email: sandeep.pande@ieee Web: birc.nuigalway.ie

SystemC Based Design Exploration of EMBRACE 1 Hardware Spiking Neural Network Architecture 1 EM ulating B iologically- inspi R ed A r C hitectures in hardwar E. Sandeep Pande and Fearghal Morgan Email: sandeep.pande@ieee.org Web: www.birc.nuigalway.ie 15 th April 2013. Outline.

wilda
Télécharger la présentation

Sandeep Pande and Fearghal Morgan Email: sandeep.pande@ieee Web: birc.nuigalway.ie

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. SystemCBased Design Exploration of EMBRACE1Hardware Spiking NeuralNetwork Architecture1EMulatingBiologically-inspiRedArChitecturesin hardwarE SandeepPande and Fearghal Morgan Email: sandeep.pande@ieee.org Web: www.birc.nuigalway.ie 15th April 2013 Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  2. Outline Spiking Neural Network (SNN) computing Paradigm EMBRACE: Network on Chip (NoC) based hardware SNN system Application of SystemC modelling, performance measurement and application evolution techniques for design of hardware SNNs SystemC performance analysis usecase: Analysis of synaptic connectivity for hardware SNNs and design of NoC for hardware SNNs Neuron modelling and for EMBRACE system design Challenges for Genetic Algorithm (GA) based hardware SNN evolution and novel parallel evolution of applications on EMBRACE-SysC (SystemC simulation model) Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  3. Biologically-Inspired Spiking Neural Network Computing Paradigm Typical Neural Network Topology Spiking Neuron Model (Leaky-Integrate-N-Fire) LIF Neuron Characteristic • Emulates real biological neural networks to realise arbitrary functions for real-life applications • Smart and adaptive solutions for complex real world problems • Generalised solution for unexplored data and operating conditions • Ideally suited to applications including data/pattern classification, estimation, prediction, dynamic control and signal processing Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  4. EMBRACE: Hardware SNN System Analogue Neuron Circuit EMBRACE Hardware SNN System • Mixed signal hardware spiking neural network architecture • CMOS-compatible analogue neuron cell Compact and low power • Network on Chip (NoC) communication infrastructure • Packet switched two-dimensional router arrayAddresses interconnect resource challenge for Hardware SNNs • Genetic Algorithm (GA)-based evolution and configuration • Easy and faster validation of architecture by SNN benchmark application evolution • Applications: • XOR, IRIS dataset classifier and inverted pendulum controller benchmark SNN applications, wisconsin breast cancer dataset classifier, bladder volume monitor and robotic navigational controller Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  5. EMBRACE: System Design Methodology EMBRACE System Design Methodology • Structured top-down system design methodology • SNN Application and hardware architecture modelling, simulation and system validation approach • SNN application feasibility • Architecture design exploration • Neuron model design and evaluation • NoC performance measurement • Faster SNN application evolution • SNN application validated architecture design Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  6. EMBRACE-SysC:SystemC based Simulation and Performance Measurement Framework EMBRACE-SysC Modelling and Simulation Flow SandeepPande, Fearghal Morgan, Seamus Cawley, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid, “EMBRACE-SysC for Analysis of NoC-based Spiking Neural Network Architectures,” International Symposium on System-on-Chip, Tampere, Finland, September 2010. • Accurate modelling of architecture and on-chip SNN data traffic • Detailed performance measurement of the system • Neuron characteristic and behaviour • Statistical NoC spike data traffic measurement • Performance comparison and analysis of architectural design choices • Faster architecture design and prototyping • Faster architecture validation using benchmark SNN application evolution Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  7. EMBRACE-SysC:NoC Performance Measurement NoC Modules (Router [x,y]) NoC Modules (Router[x,y]) NoC Modules (Router [x,y]) NoC Performance Measurement Module (Singleton Class) Router and Virtual Connection Specific Reports EMBRACE-SysCNoC Performance Measurement • EMBRACE-SysC:NoC Performance Measurement Flow: • NoC packet movement information sent to performance measurement modules • Performance measurement modules collates the NoC packet traversal based on unique IDs • NoC traffic information in the form of statistical parameters periodically Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  8. EMBRACE-SysC: Statistical NoC Performance Reporting Statistical Mesh NoC Latency Reporting Impact of NoC Latency on SNN Information SandeepPande, Fearghal Morgan, Gerard Smit, Tom Bruintjes, Jochem Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, Liam McDaid, “Fixed Latency On-Chip Interconnect for Hardware Spiking Neural Network Architectures,” Parallel Computing, Elsevier, (Under review) NoC packet latency alters spike timings and distorts SNN information Statistical NoC packet latency values used for the analysis of synpatic information distortion in SNN structures Effects of NoC packet latency variations are studied for various SNN configurations Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  9. Novel Ring TopologyNoC Architecture for EMBRACE Hardware SNN Ring Topology NoC Interconnect Ring NoC Spike Flow Control SandeepPande, Fearghal Morgan, Gerard Smit, Tom Bruintjes, Jochem Rutgers, Brian McGinley, Seamus Cawley, Jim Harkin, Liam McDaid, “Fixed Latency On-Chip Interconnect for Hardware Spiking Neural Network Architectures,” Parallel Computing, Elsevier, (Under review) • Fixed latency spike flow-control NoC interconnect • Connection topology offering fixed packet transfer latency between the source-destination nodes • Deterministic packet transmission and reception scheduling in the source and destination routers respectively • Proposed ring NoC architecture • Timestamping of spikes at the source router • Broadcasting the spike packets over the ring • Sorting the spike packets based on source timestamp at the destination router • Delivery of spikes based on timeslot counter Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  10. EMBRACE: Neuron Models EMBRACE Analogue Neuron Model for Mixed Signal Silicon Implementation EMBRACE Digital Neuron Model for Architecture Validation on FPGA SandeepPande, Fearghal Morgan, Seamus Cawley, Tom Bruintjes, Gerard Smit, Brian McGinley, Snaider Carrillo, Jim Harkin, Liam McDaid, “Modular Neural Tile Architecture for Compact Embedded Hardware Spiking Neural Network,” Neural Processing Letters, Springer, Jan 2013, doi:10.1007/s11063-012-9274-5. • Analogue neuron model for mixed signal silicon implementation • Clock cycle approximated model for faster execution speed • Membrane potential and neuron firing calculated only on spike transactions • Internal variables maintained as floating point values • Digital neuron circuit for FPGA validation • Clock cycle accurate model • Multiplier less membrane potential leakage behaviour • Internal variables maintained 8-bit integers Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  11. EMBRACE-SysC: GA-based SNN Evolution Setup EMBRACE Hardware SNN architecture and GA-based Evolution Setup • Supervised evolutionary random search method to find a correct SNN configuration (synaptic weights and thresholds) for the application SNN • Validation of architecture for suitability as embedded hardware SNN computing platform • SNN application feasibility study • Rapid application prototyping through SNN topology and configuration design Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  12. GA-based SNN Training Challenges GA-based Hardware SNN Evolution Setup Slower Operation: Evaluation of each individual SNN configuration on the SNN platform Memory Intensive: Need to store a number of SNN configurations (a population of individual SNN configurations) Bandwidth Intensive: Extensive Communication between GA-modules and the SNN platform Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  13. Faster SNN Evolution of GA-based SNN Evolution using High Performance Computing (HPC) Infrastructure EMBRACE-SysC Simulator Process 0 EMBRACE-SysC Simulator Process 1 GA Process EMBRACE-SysC Simulator Process n Multi-process, prallel GA-based Evolution of Hardware SNN SytemC Simulations Parallel evaluation of hardware SNN simulators Single GA process to maintain, configure and search SNN configurations MPI calls to communicate between GA and simulation processes Speed-up proportional to the size of SNN configuration population (x23 – x31) Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  14. Main/GA ProcessPseudo-code int main(intargc, char* argv[]) { // Initialize MPI datatypes and processes if (rank == 0) { // GA Process ... while (...) {// Sufficient SNN application accuracy ... for (...) {// All individual SNN configurations ... MPI_Isend(&command, 1, MPI_INT, i, command_tag, MPI_COMM_WORLD, &command_request); MPI_Isend(&ind_array, 1, mpi_array, i, tag, MPI_COMM_WORLD, &requestArray[i-1]); ... } MPI_Waitall(size-1, requestArray, statusArray); for (// All individual SNN configurations) { ... MPI_Recv(&recv_buf[i], 1, MPI_INT, i, tag, MPI_COMM_WORLD, &status); ... } // Generate new population of SNN configurations using evolutionary axioms (crossover, Mutation, selection) } // Send kill command to all simulator instances } else { // EMBRACE simulator instance ... sc_core::sc_elab_and_sim( argc, argv ); } MPI_Finalize(); return 0; } Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  15. EMBRACE-SysC/HSNN Simulator Pseudo-code intsc_main(intargc, char* argv[]) { // Initialize MPI datatypes and processes while (true) { ... MPI_Recv(&command, 1, MPI_INT, 0, command_tag, MPI_COMM_WORLD, &command_status); if (command == 1) { MPI_Recv(&ind_array, 1, mpi_array, 0, tag, MPI_COMM_WORLD, &status); ... // Initialize SNN modules with configuration data sc_start(l_runTime); ... // Send accuracy value to GA process MPI_Isend(&fitness, 1, MPI_INT, 0, tag, MPI_COMM_WORLD, &request); MPI_Wait(&request, &status); } else { ... return 0; } } return 0; } Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  16. Summary • Application of SystemC modelling, performance measurement and application evolution techniques for design of hardware SNNs • Statistical NoC performance analysis and design of novel NoC architecture for EMBRACE hardware SNN architecture • Early evaluation of neuron models ensures suitability ofhardware SNN architecture as embedded computing platform • Faster SNN Evolution of GA-based SNN Evolution using High Performance Computing (HPC) Infrastructure Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

  17. Acknowledgments www.icgee.ie Bio-Inspired Electronics & Reconfigurable Computing Electrical & Electronic Engineering

More Related