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ECE 448: Lab 6 Using PicoBlaze Speed Punching Game

ECE 448: Lab 6 Using PicoBlaze Speed Punching Game. Agenda for today. Part 1: Introduction to Lab 6 Part 2: Instruction Set of PicoBlaze-6 Part 3: Hands-on Session: FIDEx IDE Part 4: Lab 6 Exercise 1 Part 5: Lab 5 Demos. Part 1. Introduction to Lab 6. Sources.

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ECE 448: Lab 6 Using PicoBlaze Speed Punching Game

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  1. ECE 448: Lab 6 Using PicoBlaze Speed Punching Game

  2. Agenda for today Part 1: Introduction to Lab 6 Part 2: Instruction Set of PicoBlaze-6 Part 3: Hands-on Session: FIDEx IDE Part 4: Lab 6 Exercise 1 Part 5: Lab 5 Demos

  3. Part 1 Introduction to Lab 6 ECE 448 – FPGA and ASIC Design with VHDL

  4. Sources • P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, Picoblaze Overview Chapter 15, Picoblaze Assembly Code Development Chapter 16, Picoblaze I/O Interface Chapter 17, Picoblaze Interrupt Interface • K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6) ECE 448 – FPGA and ASIC Design with VHDL

  5. MEM_BANK: 000 001 002 . . . 0FE 0FF 100 101 102 103 104 105 106 107 108 109 1FE 1FF 7 6 5 4 3 2 1 0 A8 A8 – current memory bank number = the most significant bit of the address 255 x 8 DATA RAM BUTTON: 7 6 5 4 3 2 1 0 A BS BR BL BU BD A – button active (bit cleared by reading register BUTTON or by interrupt_ack) BS – Select, BR – Right, BL – Left, BU – Up, BD - Down MEM_BANK BUTTON PRNG_STATUS: SSD3 7 6 5 4 3 2 1 0 SSD2 D SSD1 D – done: bit cleared by writing to register PRNG_CTRL, set after PRNG generates 255 8-bit numbers SSD0 LED PRNG_STATUS PRNG_CTRL: PRNG_CTRL SWITCH 7 6 5 4 3 2 1 0 CCOUNT I I – initialize: after 1 is written to this bit, PRNG generates 255 8-bit numbers, and the corresponding address (index) of each number MEM_BANK

  6. SWITCH: 7 6 5 4 3 2 1 0 S7 S6 S5 S4 S3 S2 S1 S0 S7-S0 – bits corresponding to the state of each switch CCOUNT: 7 6 5 4 3 2 1 0 S R D R – reset the 64-bit Cycle Counter, and start counting clock cycles S – stop the Cycle Counter D – display the Cycle Counter (Switch S7 chooses between displaying Least Significant and Most Significant Word) LED: 7 6 5 4 3 2 1 0 L7 L6 L5 L4 L3 L2 L1 L0 L7-L0 – bits corresponding to the status of each LED

  7. Task 1: LCG (Linear Congruential Generator) with the period of 28-1 Rn+1 = a * Rn + c (mod m) where R is the sequence of pseudorandom values, a is the multiplier, c is the increment and m is the modulus. R0 will be the initial seed value. LCG generates one output per 1 clock cycle.

  8. Task 2 – Game • Player ID input using switches (3:0) • PRNG value divided into four 2-bit numbers, which are displayed on SSDs. • Player must press indicated buttons in the correct order. • Repeat 5 times • Completion Time is displayed on SSDs and recorded in RAM.

  9. Task 3 – Browsing Mode Address Data 00 01 02 03 04 05…. 4B 4C 4D 4E 4F …. Value at Current Address Current Address Four 7-Segment Displays (SSD0-SSD3) (in hexadecimal notation) Button 1 = Increment Address Button 0 = Decrement Address Note: press Button 3 to switch to browsing best score 128x8 RAM

  10. Task 4 – Browsing Best Score Address Data 50 51 52 53 54 55…. 73 74 75 76 77 …. Value at Current Address Current Address Four 7-Segment Displays (SSD0-SSD3) (in hexadecimal notation) Button 1 = Increment Address Button 0 = Decrement Address Note: Button 3 returns to regular browsing mode 128x8 RAM

  11. Part 2 Instruction Set of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

  12. PicoBlaze-3 Programming Model ECE 448 – FPGA and ASIC Design with VHDL

  13. PicoBlaze-6 Programming Model Bank B Bank A FFC FFD FFE FFF ECE 448 – FPGA and ASIC Design with VHDL

  14. Syntax and Terminology Syntax Example Definition sX KK PORT(KK) PORT((sX)) RAM(KK) Value at register 7 Value ab (in hex) Input value from port 2 Input value from port specified by register a Value from RAM location 4 s7 ab PORT(2) PORT((sa)) RAM(4)

  15. Addressing modes Immediate mode SUB s7, 07 ADDCY s2, 08 s7 – 07  s7 s2 + 08 + C  s2 Direct mode sa + sf  sa PORT(2a)  s5 ADD sa, sf INPUT s5, 2a Indirect mode s3 RAM((sa)) PORT((s2))  s9 STORE s3, (sa) INPUT s9, (s2)

  16. Arithmetic Instructions (1) C Z IMM, DIR Addition ADD sX, sY sX + sY => sX ADD sX, KK sX + KK => sX ADDCY sX, sY sX + sY + CARRY => sX ADDCY sX, KK sX + KK + CARRY => sX

  17. Arithmetic Instructions (2) C Z IMM, DIR Subtraction SUB sX, sY sX – sY => sX SUB sX, KK sX – KK => sX SUBCY sX, sY sX – sY – CARRY => sX SUBCY sX, KK sX – KK – CARRY => sX

  18. Test and Compare Instructions C Z TEST TEST sX, sY sX and sY => none TEST sX, KK sX and KK => none COMPARE COMPARE sX, sY sX – sY => none COMPARE sX, KK sX – KK => none IMM, DIR C = odd parity of the result IMM, DIR

  19. Data Movement Instructions (1) C Z - - LOAD LOAD sX, sY sY => sX LOAD sX, KK KK => sX IMM, DIR

  20. Data Movement Instructions (2) C Z - - DIR, IND STORE STORE sX, KK sX => RAM(KK) STORE sX, (sY) sX => RAM((sY)) - - DIR, IND FETCH FETCH sX, KK RAM(KK) => sX FETCH sX, (sY) RAM((sY)) => sX

  21. Example 1: Clear Data RAM ;========================================================= ; routine: clr_data_mem ; function: clear data ram ; temp register: data, s2 ;========================================================= clr_data_mem: load s2, 40 ;unitize loop index to 64 load s0, 00 clr_mem_loop: store s0, (s2) sub s2, 01 ;dec loop index jump nz, clr_mem_loop ;repeat until s2=0 return

  22. Data Movement Instructions (3) C Z - - DIR, IND INPUT INPUT sX, KK sX <= PORT(KK) INPUT sX, (sY) sX <= PORT((sY)) OUTPUT OUTPUT sX, KK PORT(KK) <= sX OUTPUT sX, (sY) PORT((sY)) <= sX - - DIR, IND

  23. Edit instructions - Shifts *All shift instructions affect Zero and Carry flags

  24. Edit instructions - Rotations *All rotate instructions affect Zero and Carry flags

  25. Program Flow Control Instructions (1) JUMP AAA PC <= AAA JUMP C, AAA if C=1 then PC <= AAA else PC <= PC + 1 JUMP NC, AAA if C=0 then PC <= AAA else PC <= PC + 1 JUMP Z, AAA if Z=1 then PC <= AAA else PC <= PC + 1 JUMP NZ, AAA if Z=0 then PC <= AAA else PC <= PC + 1

  26. Program Flow Control Instructions (2) CALL AAA TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA CALL C | Z , AAA if C | Z =1 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1 CALL NC | NZ , AAA if C | Z =0 then TOS <= TOS+1; STACK[TOS] <= PC; PC <= AAA else PC <= PC + 1

  27. Program Flow Control Instructions (3) RETURN PC <= STACK[TOS] + 1; TOS <= TOS - 1 RETURN C | Z if C | Z =1 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1 RETURN NC | NZ if C | Z =0 then PC <= STACK[TOS] + 1; TOS <= TOS - 1 else PC <= PC + 1

  28. Subroutine Call Flow

  29. Part 3 Hands-on Session: FIDEx IDE ECE 448 – FPGA and ASIC Design with VHDL

  30. PicoBlaze Development Environments ECE 448 – FPGA and ASIC Design with VHDL

  31. KCPSM6 Assembler Files KCPSM6.EXE ECE 448 – FPGA and ASIC Design with VHDL

  32. Directives of Assembly Language Equating symbolic name for an I/O port ID. keyboard DSIN $0E switch DSIN $0F LED DSOUT $15 N/A ECE 448 – FPGA and ASIC Design with VHDL

  33. Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

  34. Differences between Mnemonics of Instructions ECE 448 – FPGA and ASIC Design with VHDL

  35. Differences between Programs ECE 448 – FPGA and ASIC Design with VHDL

  36. Example & Demo of Tools ECE 448 – FPGA and ASIC Design with VHDL

  37. Part 4 Lab 6 Exercise 1 ECE 448 – FPGA and ASIC Design with VHDL

  38. Linear Congruential Generator (LCG) • Develop an assembly language implementation of a Linear Congruential Generator (LCG) producing a sequence of 8-bit pseudo-random numbers. • Then, use OpenPICIDE to debug and simulate your program. • Recurrence relation • Rn+1 = a * Rn + c (mod m), where • m = 28 • a=0x11 • c=0x9D • R0=0xD7 • Additionally, assume that * represents an unsigned multiplication

  39. Example ofa function in the PicoBlazeassembly language ECE 448 – FPGA and ASIC Design with VHDL

  40. Notation a Multiplicand ak-1ak-2 . . . a1 a0 x Multiplier xk-1xk-2 . . . x1 x0 p Product (a  x) p2k-1p2k-2 . . . p2 p1 p0

  41. Multiplication of two 4-bit unsigned binarynumbers Partial Product 0 Partial Product 1 Partial Product 2 Partial Product 3

  42. Unsigned Multiplication – Basic Equations k-1 x = xi  2i p = a  x i=0 k-1 p = a  x = a  xi  2i = = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1 i=0

  43. Iterative Algorithm for Unsigned Multiplication Shift/Add Algorithm p = a  x = x0a20 + x1a21 + x2a22 + … + xk-1a2k-1 = = (...((0 + x0a2k)/2 + x1a2k)/2 + ... + xk-1a2k)/2 = k times p(0) = 0 j=0..k-1 p(j+1) = (p(j) + xj a 2k) / 2 p = p(k)

  44. Iterative Algorithm for Unsigned Multiplication Shift/Add Algorithm p = a  x = x0a20 + x1a21 + x2a22 + … + x7a27 = = (...((0 + x0a28)/2 + x1a28)/2 + ... + x7a28)/2 = 8 times p(0) = 0 j=0..7 p(j+1) = (p(j) + xj a 28) / 2 p = p(k)

  45. Unsigned Multiplication Computations 8 bits 8 bits pL pH p p(j) xj a + xj a 28 + pL pH C 2 p(j+1) >> 1 p(j+1) pL pH C pH = s5 pL = s6 PicoBlaze Registers a = s3 x = s4

  46. Unsigned Multiplication Subroutine (1) ;========================================================= ; routine: mult_soft ; function: 8-bit unsigned multiplier using ; shift-and-add algorithm ; input register: ; s3: multiplicand ; s4: multiplier ; output register: ; s5: upper byte of product ; s6: lower byte of product ; temporary register: ; s2: index j ;=========================================================

  47. Unsigned Multiplication Subroutine (2) mult_soft: load s5, 00 ; clear pH load s2, 08 ; initialize loop index mult_loop: sr0 s4 ; shift lsb of x to carry jump nc, shift_prod ; x_j is 0 add s5, s3 ; x_j is 1, pH=pH+a shift_prod: sra s5 ; shift upper byte pH right, ; carry to MSB, LSB to carry sra s6 ; shift lower byte pL right, ; lsb of pH to MSB of pL sub s2, 01 ; dec loop index jump nz, mult_loop ;repeat until i=0 return

  48. Part 5 Lab 5 Demos ECE 448 – FPGA and ASIC Design with VHDL

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