1 / 15

KM3NeT CLBv2

KM3NeT CLBv2. Visual Status. IP/UDP Packet Buffer Stream Selector (IPMUX). 31 TDCs. Start Time Slice UTC & Offset counter since. Fifo. TDC0. Time Slice Start. RxPort 1. RxPacket Buffer 64KB. 31 PMTs. RxPort 2. Rx Stream Select. Fifo. TDC 30. Rx_mac2buf. Rx_buf2data. wrf_src.

willa
Télécharger la présentation

KM3NeT CLBv2

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. KM3NeT CLBv2

  2. Visual Status IP/UDP Packet Buffer Stream Selector (IPMUX) 31 TDCs Start Time Slice UTC & Offset counter since Fifo TDC0 Time Slice Start RxPort 1 RxPacket Buffer 64KB 31 PMTs RxPort 2 Rx Stream Select Fifo TDC 30 Rx_mac2buf Rx_buf2data wrf_src wrf_snk Flags RxPort_m Management & Control aux_master S State Machine Management & Config. 6 1 7 Pause Frame 5 0 4 2 Fifo ADC 3 Hydrophone TxPacket Buffer 32KB TxPort 1 TxPort 2 Tx Stream Select Tx_pkt2mac Tx_data2buf 0 1 Management & Control Flags 2 TxPort_m S S Nano Beacon ext_wb M M M S M M M M M Debug LEDs WB Crossbar (1x7) WB Crossbar (3x2) S S S S S M M M GPIO I2C 2nd CPU LM32 I2C SPI UART Xilinx Kintex-7 S MEM S M S M Data UTC time & Clock (PPS+RefClk) Compass Debug RS232 Temp Tilt SPI Flash Control Point to Point interconnection Wishbone bus

  3. Status Listing • Done: • LM32 + WB-Crossbar + DPRAM + UART • Soft-PLL FMC layout • WR without PCI-express • Deterministic PHY • 1-wire • Currently: • Soft PLL (hardware + software). Still under study… • Endpoint (= MAC) <= underinvestigation, focus on user interface • Fabric redirector <= focus on user interface • To do (in order of priority): • Mini-nic <= Complex, but seems to work (PTP flows) • PPS generator <= relatively straightforward • SysCon <= easy?

  4. KC705 WR Ethernet port Block diagram Ethernet MAC wrf_src wrf_snk aux_master (Etehrbone) 1 6 7 5 0 4 2 3 0 1 2 1 Ethernet traffic: PTP frames 0 0 1 2

  5. Connect IPMUX=> WRPC simulation IPMUX Frame Generator • Already reported last meeting (August 22, 2013): • Initialize the Endpoint registers and memory • Co-simulation of hardware & software (wrc.elf)

  6. Endpoint investigation 1ep_rx_path • Packet filter didn’t work properly • No MAC address match because of one pipeline stage mismatch • A newer version for “ep_packet_filter.vhd” was found in the repositorythat does the proper match! xwrf_mux (= Fabricredirector) 1 0 2 3 4 5 7 8 9 1 6 fab_pipe IPMUX ep_rx_early_address_match ep_rx_status_reg_insert ep_rx_buffer ep_packet_filter ep_clock_alignment_fifo ep_rx_oob_insert ep_rx_crc_size_check ep_rx_vlan_unit ep_rtu_header_extract ep_rx_wb_master 0 xwr_mini_nic

  7. Endpoint investigation 1 • Conclusion the White Rabbit PTP Core Release v2.0 tarball is a non coherent set of files! • Many more files are updated. (A lot of bug fixes have been donesince v2.0) • Downloaded the newest files from the WR git repository, made minor KM3NeT changes andplacedtheminto SVN • Wrpc-sw Software alsoneedstobeupdatedand setup for KC705 use => Mieke Bouwhuis

  8. New set of WRPC filesPackets received! • 7 ping sent • 7 received • No replay since “WITH_ETHERBONE=0” • Ourown IP/UDP packet do not increment the RX counter sincethispacket does not flow thru the mini-nic!

  9. Endpoint investigation 2ep_rx_path • CRC-errors occurred in the endpoint because the Ethernet frame generator (simulation) produces the wrong CRC (due to 8/16 bit CRC calculation). xwrf_mux (= Fabricredirector) 1 0 2 3 4 5 7 8 9 1 6 fab_pipe IPMUX ep_rx_early_address_match ep_rx_status_reg_insert ep_rx_buffer ep_packet_filter ep_clock_alignment_fifo ep_rx_oob_insert ep_rx_crc_size_check ep_rx_vlan_unit ep_rtu_header_extract ep_rx_wb_master 0 xwr_mini_nic

  10. Endpoint investigation 3; Bug? -- MAC Source andDestinationAddressand Ethernet Type-II FrameData.Frames(1, 0) := MAC_Dst(47 downto 32); FrameData.Frames(1, 1) := MAC_Dst(31 downto 16); FrameData.Frames(1, 2) := MAC_Dst(15 downto 0); FrameData.Frames(1, 3) := MAC_Src(47 downto 32); FrameData.Frames(1, 4) := MAC_Src(31 downto 16); FrameData.Frames(1, 5) := MAC_Src(15 downto 0); FrameData.Frames(1, 6) := x"0800"; -- IP Header FrameData.Frames(1, 7) := x"4500"; FrameData.Frames(1, 8) := x"0026"; FrameData.Frames(1, 9) := x"0000"; FrameData.Frames(1, 10) := x"0000"; FrameData.Frames(1, 11) := x"8011"; --check sum FrameData.Frames(1, 12) := x"B771"; --end check sum FrameData.Frames(1, 13) := x"C0A8"; FrameData.Frames(1, 14) := x"0102"; FrameData.Frames(1, 15) := x"C0A8"; FrameData.Frames(1, 16) := x"0103"; -- UDP Header FrameData.Frames(1, 17) := x"2000"; FrameData.Frames(1, 18) := x"1000"; FrameData.Frames(1, 19) := x"0012"; FrameData.Frames(1, 20) := x"0000"; -- Payload FrameData.Frames(1, 21) := x"0C00"; FrameData.Frames(1, 22) := x"1700"; FrameData.Frames(1, 23) := x"0000"; FrameData.Frames(1, 24) := x"0000"; FrameData.Frames(1, 25) := x"0000"; -- Padding FrameData.Frames(1, 26) := x"0000"; FrameData.Frames(1, 27) := x"0000"; FrameData.Frames(1, 28) := x"0000"; FrameData.Frames(1, 29) := x"0000"; Length is okay Length is one short Wrf_src_i: Should have been 0x0000!? Is this a bug in ep_rx_bypass_queue.vhd? => Needstobesorted out! 4 5 fab_pipe ep_rx_crc_size_check

  11. Endpoint <-> ipmux • ipmuxneeds more modificationthanexpected… • No rocketscienceinvolved but… • … it takes time.

  12. General: endpoint, ipmux • Simulationnow up and running. • IP/UDP packets flow thruendpoint • Need to check if last word of the packet lost? • First shot (streaming wishbone b4) wrf_source -> ipmux_sink made... Thorough verification needed. • Integrate clb_wrpc and ipmux. The design / simulation is getting big...

  13. Timing Servo No “TRACK_PHASE” yet No valid EEPROM image withcalibration parameters in our case. Mieke Bouwhuis studies this issue

  14. PHY RXCDRLOCK_OUT • Xilinx webcase answer from Erik Schidlack: • “You cannot use the RXCDRLOCK output to check that the receiver is locked to data. This is only a coarse indicator and it is marked as reserved in the user guide too. Please check the incoming data stream to get this information. You should check for expected data.” • “The behaviour you see now in simulation can happen in hardware too. It will be even more common. The signal will go low when the phase offset of the incoming data is greater than the current lock window of the CDR. This window is adapting to the signal and this situation can happen under normal circumstances when you still receive correct data.” • My answer: • “Checking for expected incomming data is only functional when you know what is to be expected, which is the case for idles but not for ordinairy data.” • Workaround implement a digital filter, such that you only de-assert cdr lock when RXCDRLOCK gets de-asserted for at least "n" clock cycles. • How big should "n" be? (currently set to “3”)

  15. Summary WR status • Focus on ipmux connection to WR • Understand Endpoint and wr fabric sink and source => simulation • Timing Servo (still) does not lock => PPS not enabled (but focus now on ipmux connection). • Servo State: “Uninitialized” => “SYNC_SEC” => “SYNC_NSEC“ • …but not yet “SYNC_PHASE” and “TRACK_PHASE” • PHY RXCDRLOCK_OUT => workaround

More Related