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L OW C OST TDRSS T RANSCEIVER (LCT2)

W ALLOPS F LIGHT F ACILITY E LECTRICAL E NGINEERING B RANCH C ODE 569. L OW C OST TDRSS T RANSCEIVER (LCT2). Transmitter CDR A PRIL 2004. LCT2 Transmitter. Agenda Review Board System Transmitter Design Subsystem Designs Packaging Thermal Analysis Conclusion. Review Board.

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L OW C OST TDRSS T RANSCEIVER (LCT2)

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  1. WALLOPS FLIGHT FACILITY ELECTRICAL ENGINEERING BRANCH CODE 569 LOW COST TDRSS TRANSCEIVER (LCT2) Transmitter CDR APRIL 2004 Wallops Flight Facility - Code 569

  2. LCT2 Transmitter • Agenda • Review Board • System • Transmitter Design • Subsystem Designs • Packaging • Thermal Analysis • Conclusion Wallops Flight Facility - Code 569

  3. Review Board • Steven Kremer • Chair - WFF Range and Mission Management Office • Major Nick Chando • USAF Det 12 • David Gregory • WFF Balloon Program Office • Wayne Powell • WFF Chief Technologist • David Weeks • MSFC Exploration and Development Office Wallops Flight Facility - Code 569

  4. System - Requirements • Functional • Modulation: BPSK/QPSK, TDRSSDG1 Mode 2 or non-spread • Freq. Range: 2205 – 2295 MHz • Dual or single channel • Performance • 10 W RF output (support for 5 W or 30 W modules) • Bit Rate: PN/BPSK 300 kbps (150 kbps w/ conv encoding), 6 Mbps QPSK non-spread • Physical • Small form-factor, < 2 lbs, Sounding rocket environment • Electrical • 22 – 32 VDC input, < 100 W for 10 W RF Output Wallops Flight Facility - Code 569

  5. System - Design Approach • Direct RF Modulation vs. Digital Modulator Trade Off • Compact Form-factor • Integrated RF/Digital PCB • Industrial Grade Parts • Low Power • Re-configurable FPGA architecture Wallops Flight Facility - Code 569

  6. Trade Study • Direct RF Modulation or Digital Modulation • Preliminary design was Direct RF Modulator • Evaluated Code 567 Microwave Systems Branch digital modulator design • Utilize VHDL design from SDR development • Trade Offs • Direct RF Modulator: no mixing components, SAW filter not required, supports higher data rates in future ( > 100 Mbps) • Digital Implementation: Flexibility, capable of supporting other modulation schemes • Decision to Implement Both • Reduce Design Risk • Utilize Higher Performing Modulation Scheme • Provides flight test bed for SDR development Wallops Flight Facility - Code 569

  7. System Capabilities • BPSK or QPSK Modulation • TDRSS DG1 mode 2 (MA) • Digitally synthesized IF (higher order mod schemes) • > 100 Mbps analog QPSK modulation • RS422 clock & data synchronous inputs • RS232 asynchronous data input • RS232 status and control • 12 W RF S-Band Output • 4” x 5” x 1.38” size • 1.5 lbs weight max • Rugged form-factor • 20 G’s (Sounding rocket qual) • -24° C to +65 ° C Wallops Flight Facility - Code 569

  8. Block Diagram Wallops Flight Facility - Code 569

  9. Interfaces • Inputs • Clock & Data • 2 RS422 • 1 RS232 Asynchronous Data • Status & Control • 1 RS232 (Reconfigurable for testing & debug) • 22 – 32 VDC Power • Discretes: Transmitter on/off • Outputs • RF Output (SMA) • Discretes: Tx Fwd & Rev Power Monitor Signals, Temperature Wallops Flight Facility - Code 569

  10. FPGA Wallops Flight Facility - Code 569

  11. FPGA • Digital Modulation BPSK or QPSK • IFOutput Frequency: 70 MHz • Data encoding • Differential (NRZ-L to M) • Convolutional (R=1/2, k=7) • Status via RS232 • Output Power, Reflected Power & System Temperature • Control via RS232 • BPSK/QPSK select, Encoding on/off, Spreading on/off, RF frequency, Spreading PN code & Analog/Digital modulation select • Asynch to sync conversion for modulating RS232 data stream • Gold code generator • Waveform shaping for analog modulator • Control registers can be configured to route test points to external interface Wallops Flight Facility - Code 569

  12. FPGA • FPGA Selection - Xilinx XC2V1000-5FG256I • Virtex II family • 1,000,000 gates • Wire-bond, fine-pitch ball grid array (BGA) • 172 available I/Os • Speed grade 5 (fastest for industrial version) • 8 Digital clock managers (DCM) • Frequency synthesis • Manages clock de-skew • 40 Dedicated 18 x 18 bit multipliers Wallops Flight Facility - Code 569

  13. FPGA • Digital Modulator • VHDL Code developed on Xilinx ISE 6.2i • Modeled and code generated by Xilinx System Generator in Matlab Simulink • DCM generates 80 MHz sample clock from 10 MHz reference input • 14 bit output to DAC • Can bypass modulator to provide filtered baseband output Wallops Flight Facility - Code 569

  14. FPGA • Digital Modulator Wallops Flight Facility - Code 569

  15. FPGA • Digital to Analog Converter • Analog Devices AD9772A • 14 bit resolution • 2x interpolation filter • High pass filter select to pass 1st image for direct IF applications. • 80 MHz sample rate - 10 MHz synthesized modulation = 70 MHz IF • Zero stuffing option to improve flatness in IF band Wallops Flight Facility - Code 569

  16. Upconverter Wallops Flight Facility - Code 569

  17. Upconverter • Upconverter (Digital modulation mode) • 70 MHz IF from DAC input to Sawtek 10 MHz BW bandpass filter • IF upconverted to S-Band utilizing Hittite HMC422MS8 mixer • LO frequency programmable Wallops Flight Facility - Code 569

  18. Local Oscillator (LO) Wallops Flight Facility - Code 569

  19. Local Oscillator (LO) • Local Oscillator Generator • 10 MHz reference oscillator • Piezo Technology XO3080 • ± 1 ppm temperature stability, -55o to +85o C • NS LMX2326 2.8 GHz Freq. Synthesizer • Zcomm V800ME09 VCO • Prototype module built for stability measurements Wallops Flight Facility - Code 569

  20. Local Oscillator (LO) • LO Thermal Stability Performance Temperature LO Frequency Wallops Flight Facility - Code 569

  21. Direct RF Modulator (Analog) Wallops Flight Facility - Code 569

  22. Direct RF Modulator (Analog) • Direct RF Modulation (Analog) • Analog Devices AD8346 • 0.8 to 2.5 GHz frequency range • DC – 70 MHz modulation BW • 1 deg. rms phase imbalance • 0.2 dB I/Q amplitude imbalance • Modulation input from DAC or pre-mod filtered data directly out of FPGA • LO input to modulator at actual S-band frequency Wallops Flight Facility - Code 569

  23. Output Spectrum • Spectrum Plots Wallops Flight Facility - Code 569

  24. Modulator PCB • Digital components and RF components isolated on opposite sides • Board level debug capability • High density connector • Prototype for receiver • Interface to future integrated modules (GPS, INS, etc.) • Digital Side • FPGA, DAC’s, ADC’s, DDS • FPGA thermal, mechanical configuration • Cold finger attached to enclosure wall for heat transfer • Epoxy underfill for thermal and mechanical ruggedness • RF Side • RF synthesizer, Saw filter, Upconverter & Direct modulator Wallops Flight Facility - Code 569

  25. Modulator PCB • 12 Layer board Wallops Flight Facility - Code 569

  26. Modulator PCB • Digital Side - Component Layout • 3.75” x 3.25” Wallops Flight Facility - Code 569

  27. Modulator PCB • RF Side - Component Layout Wallops Flight Facility - Code 569

  28. Power Amplifier Wallops Flight Facility - Code 569

  29. Power Amplifier • Capabilities • Fujitsu FMM5049VT MMIC amplifier • Pout = 41.0 dBm ( 12.6 W) • 33.0 dB linear gain • 1.8 – 2.3 GHz frequency band • 32 % efficiency Wallops Flight Facility - Code 569

  30. Power Amplifier • 4 Layer PCB Rogers and FR-4 layer • Driver amplifier between modulator board and PA • RF Bandpass filter on input to suppress mixing components in digital modulation mode • Coupler • Provides output forward & reflected power samples • Power detectors provide inputs to ADC for forward/reflected power status • Temperature sensor for monitoring Wallops Flight Facility - Code 569

  31. Power Amplifier • Power Amplifier Layout • 3.75” x 1.25” Wallops Flight Facility - Code 569

  32. Power Amplifier • Signal Level Analysis Wallops Flight Facility - Code 569

  33. System Power Wallops Flight Facility - Code 569

  34. System Power • Single 22 – 32 VDC input • 2 Datel DC-DC converters for better efficiency • 1 unit dedicated to modulator board • 1 unit dedicated to power amp module • Describe power distribution and regulator configuration here Wallops Flight Facility - Code 569

  35. Packaging • Design Objectives • Minimize size • Minimize mass • Minimize cost • Maximize robustness Wallops Flight Facility - Code 569

  36. Packaging • Environmental Requirements • Pressure range: from one atmosphere to 1 x 10 -5 Torr • Operating temperature range: -24˚ to +65 ˚C • Structural and Mechanical: random vibe, sine sweep, shock, and static acceleration • Relative humidity: 0 to 90% in the range +5 to +45 ˚C • EMC Wallops Flight Facility - Code 569

  37. Packaging • Design Methodology • Size the system based on electrical requirements • Mount high thermal flux components near the base or walls of the enclosure to minimize component temperatures • FPGA placed near board edge to minimize thermal path to the enclosure • Use thermal and dynamic FEA models to guide component placement and determine suitable interface materials • Power, I/O, and RF connector placement restricted to enclosure side-walls to enable stacking Wallops Flight Facility - Code 569

  38. Packaging • Package Design Details • Transmitter package size: 4” x 5” x 1.44” (100 x 125 x 36.5 mm) • Transmitter mass: ~1.5 lb (0.68 kg) • Heat dissipation: 65 W (for 10 W transmitter) • Electrical interfaces: I/O, power input, and RF output • Segregated RF and Digital enclosure compartments • Enclosure emulates COMPAC RFT series design • Enclosure material: 6061-T6 aluminum • Vented hardware used for depressurization and to prevent virtual leaks • All materials meet NASA outgassing specs (TML < 1%, CVCM < 0.1%) Wallops Flight Facility - Code 569

  39. Packaging • Package Dimensions LCT2 Package NOTE: Dimensions are in inches Weight: 1.5 lbs Wallops Flight Facility - Code 569

  40. RF Output Packaging • System Level Mechanical, Thermal, and Electrical Interfaces Mounting Plate (Keratherm Interface) Power Input I/O Connections Wallops Flight Facility - Code 569

  41. Packaging • Package Layout Modulator board Power Amp Board Power and RF feedthroughs Wallops Flight Facility - Code 569

  42. Packaging • Primary Heat dissipating Components Cold Strap FPGA (1.2 W) Power Amp (30 W) DC-DC converters (12 W) Voltage regulators (22 W) Wallops Flight Facility - Code 569

  43. Voltage Regulator Power Amp Indium Nut Kapton Kapton (type MT) Packaging • Component Level Thermal Interfaces DC-DC Converter Keratherm Wallops Flight Facility - Code 569

  44. Indium (interface between strap and enclosure wall) Epoxy under-fill Thermally conductive epoxy Braided Cold Strap Packaging • FPGA Thermal Interface Wallops Flight Facility - Code 569

  45. Thermal Analysis • Introduction • The LCT2 assembly was studied using Finite Element Analysis (FEA). • Analysis was conducted in parallel with the mechanical package layout to guide both component specification and placement. • Thermal modeling was the focus though some mechanical load conditions were considered as well. • The LCT2 Design Requirements description of Qualification Testing procedures was used to specify model load conditions. Wallops Flight Facility - Code 569

  46. Thermal Analysis • FEA Model Components Wallops Flight Facility - Code 569

  47. Thermal Analysis • Finite Element Model Geometry • The major components are explicitly modeled. Wireframe Solid 0.75” thick Al Plate 15.5” diameter Wallops Flight Facility - Code 569

  48. Thermal Analysis • Power Amp PCB Sub Model FEA Mesh XY Loading Z Loading Wallops Flight Facility - Code 569

  49. Thermal Analysis • Modulator PCB Sub Model FEA Model Z Loading XY Loading Wallops Flight Facility - Code 569

  50. Thermal Analysis • FPGA Underfill Sub Model A portion of the FPGA BGA was explicitly modeled to approximate its average out-of-plane (z) conductivity. ½ mm diameter balls (Sn-Pb solder) on a 1mm Pitch were modeled along with thermally conductive epoxy backfill. Wallops Flight Facility - Code 569

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