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MCP 1

Gate IN. T979 Logic Diagram 4/29/08. CFD IN. Enable IN. 4300 ADC. CFD IN. 4302 MEM. FERA OUT. FERA IN. Ramp IN. Timing OUT. Start IN. Timing OUT. Timing IN. Enable IN. 9327 CFD. 566 TAC. AD114 ADC. MCP 4. PC. Overflow OUT. Monitor OUT. Stop IN. Gate IN. FERA OUT.

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MCP 1

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  1. Gate IN T979 Logic Diagram 4/29/08 CFD IN Enable IN 4300 ADC CFD IN 4302 MEM FERA OUT FERA IN Ramp IN Timing OUT Start IN Timing OUT Timing IN Enable IN 9327 CFD 566 TAC AD114 ADC MCP 4 PC Overflow OUT Monitor OUT Stop IN Gate IN FERA OUT Timing OUT Start IN Timing OUT Timing IN Enable IN MCP 3 9327 CFD 566 TAC AD114 ADC Monitor OUT Stop IN Gate IN FERA OUT Timing OUT Timing 2 IN FERA OUT Scint 4 Disc 3377 TDC Com Stop IN Timing OUT 365AL Logic Timing 1 IN Timing OUT Scint 3 Disc Timing OUT Gate OUT 365AL Logic 2323 Delay/ Gate VETO IN Event VETO Gate OUT Fan In/Out (OR Gate) 365AL Logic Spill VETO Gate IN Overflow OUT Reset Ramp IN Enable IN 4300 ADC Signal OUT 4302 MEM Ramp Pulser CFD IN FERA OUT FERA IN Signal OUT CFD IN Timing OUT Start IN Timing OUT Timing IN Enable IN 9327 CFD 566 TAC AD114 ADC MCP 2 Monitor OUT Stop IN Gate IN FERA OUT Timing OUT Start IN Timing OUT Timing IN Enable IN MCP 1 9327 CFD 566 TAC AD114 ADC Monitor OUT Stop IN Gate IN FERA OUT Timing 2 IN Timing OUT FERA OUT Scint 2 Disc 3377 TDC Com Stop IN Timing OUT 365AL Logic Timing 1 IN Timing OUT Scint 1 Disc Timing OUT Timing 3 IN ID Timing OUT BEAM

  2. Jerry’s modification: HPK’ amp QTNT FERA 4300 ADC 9327 CFD AD114 ADC MCP 2 566 TAC MCP 1 9327 CFD HPK’ amp QTNT Event VETO Event Gate

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