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A new m  e g experiment at PSI

A new m  e g experiment at PSI. For the MUEGAMMA collaboration Stefan Ritt (Paul Scherrer Institute, Switzerland). Introduction Experimental Technique New Electronics Current status. Physics Motivation. SUSY theories generically predict LFV LFV forbidden by Standard Model

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A new m  e g experiment at PSI

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  1. A new m e g experiment at PSI For the MUEGAMMA collaboration Stefan Ritt (Paul Scherrer Institute, Switzerland) • Introduction • Experimental Technique • New Electronics • Current status

  2. Physics Motivation • SUSY theories generically predict LFV • LFV forbidden by Standard Model • Processes like m+ e+g are not “contaminated” by SM processes and therefore very clean • Discovered n oscillations are expected to enhance LFV rate • The search for m+ e+g is therefore a promising field to find physics beyond the SM

  3. Prediction from SUSY SU(5) ft(M)=2.4 m>0 Ml=50GeV 1) Current experimental bound 2) This experiment • J. Hisano et al., Phys. Lett. B391 (1997) 341 • MEGA collaboration, hep-ex/9905013

  4. Connection with n oscillations1) 2) This experiment • J. Hisano and D. Nomura, Phys. Rev. D59 (1999) 116005 • MEGA collaboration, hep-ex/9905013

  5. Previous m+e+g Experiments • New experiment: 10-14 at PSI • Letter of Intend 1998 • Proposal 1999, approved May 1999

  6. MEG Collaboration 35 7

  7. Kinematics qeg= 180° g e m Ee = 52.8 MeV Eg = 52.8 MeV Experimental Method • Stopped m beam of 108 s-1, 100% duty factor • Liquid Xe calorimeter for gdetection • Solenoidal magnetic spectrometer with gradient field • Radial drift chambers for e+ momentum determination • Timing counter for e+

  8. meg g m e m e Signal and Background • m+ e+g signal very clear • Eg = Ee+ = 52.8 MeV • qge+ = 180° • e+ and g in time • Background • Radiative m+ decays • Accidental overlap • Detector Requirements • Excellent energy resolution • Excellent timing resolution • Good angular resolution menng menn + g g n g m n e e m

  9. Y = Eg/52.8MeV X = Ee/52.8MeV meg Signature •  eg Ee,Eg = 52.8MeV •  egnn Ee,Eg < 52.8MeV

  10. Sensitivity and Background Rate BR(meg) = (Nm• T • W/4p• ee• eg• esel )-1 = 0.94  10-14 Prompt Background Bpr 10-17 Accidental Background Bacc DEe • Dteg • (DEg )2• (Dqeg )2  5  10-15

  11. Paul Scherrer Institute Experimental Hall

  12. Experimental Hall

  13. Sindrum II @ PSI Bue=4 •10-12 m-Ti  e-Ti : Oct. 2000 (50d) beam time: 90% C.L. limit: 6.1• 10-13

  14. pE5 Beam Line • 108m/s on 55 mm2 • Neutron background measured in 1998 • Two Beam tests in 2002

  15. Detector

  16. H.V. Refrigerator Signals Cooling pipe Vacuum for thermal insulation Al Honeycomb Liq. Xe window PMT filler Plastic 1.5m LXe Calorimeter • ~800l liquid Xe (3t) • ~800 PMTs immersed in LXe • Only scintillation light detected • Fast response (45 ns decay time) • High light output (70% of NaI(Tl))1) • High uniformity compared with segmented calorimeters • High channel occupancy will be accommodated by special trigger scheme 1) T. Doke and K. Masuda, NIM A 420 (1999) 62

  17. g Response • Signal is distributed over many PMTs in most cases • Weighted mean of PMTs on the front face  dx ~ 4mm FWHM • Broadness of distribution  dz ~ 16mm FWHM • Timing resolution  dt ~ 100ps FWHM • Energy resolution ~ 1.4% FWHMdepends on light attenuation in LXe x z

  18. Calorimeter Prototypes “Small” “Large” • 32 PMTs, 2.3 l LXe • Tested with radioactive sources 51Cr, 137Cs, 54Mn, 88Y • Extrapolated resolutions at 52.8 MeV in agreement with quoted numbers Measure resolutions with 40 MeV photon beam at ETL, Tsukuba, Japan

  19. Large Prototype • Currently largest LXe detector in the world (224 PMTs, 150l), • Contains all critical parts of final detector

  20. Homogeneous Field Gradient Field (COnstant-Bending-RAdius) Positron Spectrometer e+ from m+e+g Ultra-Thin (~3g/cm2) superconducting solenoid with 1.2 T field

  21. Drift Chamber • 16 radial chambers with 20 wires each • Staggered cells measure both position and time • He – C2H6 gas to reduce multiple scattering • Vernier pattern to determine z coordinate

  22. Prototype Test at PSI • 0, 0.6, 0.8, 1T field • 3 tilting angles • Chamber ok, electronics needs improvement

  23. Thin Superconducting Coil g Stopping Target Muon Beam Timing Counter e + Drift Chamber Positron timing counter • Aimed resolution ~100ps FWHM • Beam tests at KEK in July 1999 • Taken over by Pisa group • Tests with cosmic m confirmed 100ps FWHM http://meg.psi.ch/ subprojects/tcount/

  24. Kinematics qeg= 180° m g e Ee = 52.8 MeV Eg = 52.8 MeV Trigger Requirements • Total ~800 PMTs • Common noise contributes significantly to analog sum • AC coupling  Baseline drift • How to evaluate q,f of shower center? • Beam rate 108 s-1 • Fast LXe energy sum > 45MeV 2103 s-1 • g interaction point • e+ hit point in timing counter • time correlation g – e+ 200 s-1 • angular corrlation g – e+ 20 s-1 M.C.

  25. Digital Trigger 10bit / 100MHz FADC 3.3V 2.5V VME Interface (Cypress) LVDS 3.3V 2.5V VME Interface (Cypress) FADC LVDS 8 channels FADC FPGA LVDS FPGA FADC LVDS FADC FPGA LVDS FPGA SRAM SRAM FADC LVDS 8 channels FADC LVDS FADC LVDS FPGA SRAM FPGA SRAM LVDS LVDS FPGA LVDS FPGA LVDS LVDS LVDS LVDS LVDS LVDS clck, clear 48 bits output

  26. Baseline Subtraction Baseline Subtraction 100 MHz Clock 10 bit Latch Latch Latch Latch Calibrated and linearized signal Baseline subtracted signal + Latch LUT 10x10 S - S S - + Uses ~120 out of 5000 logic cells  8 channels/FPGA use 20% of chip S S Latch Baseline Register <thr

  27. QT Algorithm original waveform t • Inspired by H1 Fast Track Trigger (A. Schnöning) • Difference of Samples (= 1st derivation) • Hit region defined when DOS is above threshold • Integration of original signal in hit region • Pedestal evaluated in region before hit • Time interpolated using maximum value and two neighbor values in LUT  1ns resolution for 10ns sampling time Region for pedestal evaluation integration area smoothed and differentiated (Difference Of Samples) Threshold in DOS

  28. Trigger latency ADC BS S ADC BS S >45MeV ADC BS S ADC BS . . . AND . . . . . . Max Max Df Max fe+ 10 stages = 1024 chn T[ns] 0 50 100 110 120..200 220 230 Inter-board communication: 120 ns Total latency: 350 ns

  29. Prototype board FPGA Signal- Generator ADC DAC

  30. m e DAQ Requirements n PMT sum 0.511 MeV meg Michel edge 51.5 MeV 50 51 52 E[MeV] t ~100ns (menn)2 + g • g’s hitting different parts of LXe can be separated if > 2 PMTs apart (15 cm) • Timely separated g’s need waveform digitizing > 300 MHz • If waveform digitizing gives timing <100ps, no TDCs are needed g e m

  31. pb Domino Sampling Chip • 0.5 – 1.2 GHz sampling speed • 128 sampling cells • Readout at 5 MHz, 12 bit • ~ 100 CHF/channel • Needed: • 2.5 GHz sampling speed • Circular domino wave • 1024 sampling cells • 40 MHz readout • < 100ps accuracy C. Brönnimann et al., NIM A420 (1999) 264

  32. input Domino Ring Sampler (DRS) • Free running domino wave, stopped with trigger • Sampling speed 2 GHz (500ps/bin) • Readout 40 MHz 12 bit • 1024 bins  150ns waveform + 350ns delay

  33. DAQ Board • 9 channels  1024 bins / 40 MHz = 230 ms  acceptable dead time • Zero suppression in FPGA • QT Algorithm in FPGA (store waveform if multi-hit) • Costs per channel: ~25$ (board) + 6$ (chip) 8 channel DRS 3.3V 2.5V VME Interface (Cypress) 40 MHz 12 bit 8 channel DRS FPGA FADC 8 inputs FADC 8 channel DRS SRAM FPGA 8 channel DRS FPGA FADC SRAM Trigger Input SRAM shift register trigger gate 3 state switches Board inter-connect SRAM SRAM Trigger BUS (2nd level tr.)

  34. TDC Disc. Scaler ADC Scope “Redefinition” of DAQ DSC ~GHz FADC 100 MHz FPGA SRAM

  35. Cryogenics Design

  36. ADuC812 / C8051F000 Micro controllers with 8x12 bit ADC, 2x12 bit DAC RS485 bus over flat ribbon cable Powered through bus Costs ~30$ Piggy back board New slow control system Generic node

  37. Generic node with signal conditioning Sub-master with power supply and PC connection (Parallel Port, USB planned) Integration on sensors, in crates RS232 node planned 2 versions BUS Oriented Crate Oriented • 19” crate with custom backplane • Generic node as piggy-back • Cards for analog IO / digital IO / °C / 220V • crate connects to parallel port (USB)

  38. Midas Slow Control Bus • 256 nodes, 65536 with one level of repeaters • Bus length ~500m opto-isolated • Boards for voltage, current, thermo couples, TTL IO, 220V output • Readout speed: 0.3s for 1000 channels • C library, command-line utility, Midas driver, LabView driver • Nodes are “self-documenting” • Configuration parameters in EEPROM on node • Node CPU can operate autonomously for interlock and regulation (PID) tasks (C programmable) • Nodes can be reprogrammed over network http://midas.psi.ch/mscb

  39. Time Table now Planning R & D Assembly Data Taking 1997 1998 1999 2000 2001 2002 2003 2004 2005 2006 2007 Conclusions • Preparations are going well in all areas of the experiment • Innovative technologies developed useful for other experiments • Next major milestone: Large prototype test in Tsukuba spring 2002 http://meg.psi.ch

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