Nanoelectronic and Nanophotonic Interconnect

1. Nanoelectronic and Nanophotonic Interconnect Hyun-Yong Jung High-Speed Circuits and Systems Laboratory

2. Outline • Introduction • The ITRS interconnect road map • The nanophotonic partition length • Global photonic interconnect architectures • Components for local photonic interconnect • Nanophotonic waveguides and resonators • for global interconnect • Conclusions

3. Introduction • Five-level hierarchy of limits • Fundamental • Material • Device • Circuit • System • Technology scaling : Moore’s law •  The number of transistors that can be placed on an integrated circuit has doubled approximately every 18 months

4. Introduction • A 10-nm minimum feature size could support a chip with more than 100 billion transistors sometime beyond 2020, if we can, • Develop 10-nm-scale fabrication technologies that will circumvent the expected exorbitant manufacturing costs arising from optical lithographic technologies • Devise effective methods to handle the necessarily large number of defective components that will be present in such circuits • Handle the heat dissipation from the projected power densities • Invent the necessary global interconnect technology to effectively complement 10-nm transistors • Copper, carbon nanotubes….. •  Integrated nanoscale electronic-photonic circuits!

5. The ITRS interconnect roadmap • ITRS – International Technology Roadmap for Semiconductors •  Provides direction for all companies that participate in the process and points out the areas where research is urgently needed in order to overcome the biggest obstacles to a particular generation of product • organizations and companies participate in formulating the road map • Reformulated every other year • (odd years) • Revised in the intervening • (even) years

6. The ITRS interconnect roadmap • Frequent comments such as (2005 and/or 2006 ITRS): •  “This dramatic reversal from performance limited by transistor delay to performance limited by interconnect delay shows clearly the inadequacy of continuing to scale the conventional metal/dielectric system to meet future interconnect requirements.” • The interconnect stack of a CMOS integrated circuit • 1. Direct : Metal 1, connection to the semiconductor level • 2. Intermediate : Next 2~8 levels of interconnect • 3. Global : Top 2~5 levels in the hierarchy • Problems • 1. RC time constant is proportional to the square of the length <R,C > • 2. Widths of the interconnect  RC time constant per unit length

7. The ITRS interconnect roadmap • Photonic Interconnect Comparison for 2006 ITRS Goals • 2006 ITRS revision(highlighted in blue) • A set of quantities derived from the roadmap data(highlighted in green)

8. The ITRS interconnect roadmap • Bit hop length : 719 um in 2007  49 um in 2020 • The number of transistor : 6 million in 2007  0.5 million in 2020 • The transistor density will not increase rapidly

9. The ITRS interconnect roadmap • 1.4 mW in 2007 – given that there are approximately 60000 such lines in a chip •  Easy to see that without careful management • 0.17 mW in 2020 – the sheernumber of such lines (many millions) would • require kilowatts of power  No current cooling technology to handle • ITRS assumes that it will be possible to decrease the dielectric constant of the insulating layers in the chip to 2  would be hard

10. The nanophotonic partition length • Wmin = minimum wire width, waveguide width • Ko = 6.152 Χ 1016 Hz • fmax = maximum modulation frequency • Partition length •  More effeciently transported by photons rather than electrons • Partition length •  Above 20 GHz, the partition length for a wire/waveguide width of 1 um is less than 2 mm

11. The nanophotonic partition length • Wmin = minimum wire width, waveguide width • Ko = 6.152 Χ 1016 Hz • fmax = maximum modulation frequency • N = Channel (OWDM) • OWDM = Optical wavelength-division multiplexing • Partition length • Above 20 GHz, the partition length for a wire/waveguide width of 1 um carrying 30 channels is less than • 60 um • Roughly equal to the electronic “bit hop length” in 2020

12. The nanophotonic partition length • Advantages for optical interconnect • No capacitive charging & discharging losses for photonic bits • The energy required to transmit a bit over a long distance is much lower for the photonic interconnect • Greatly increase the data bandwidth over an all-electrical interconnect • Disadvantages for optical interconnect • Generating the photons on the chip will require a huge amount of power • Generating photons off chip • Limited by the wavelength of light •  Photonic crystal s may allow researchers to reach optoelectronic feature sizes as small as λ/10 and devices capable of operating at light levels of only a few photons “High level of integration” of photonic functional devices could occur

13. Global photonic interconnect architectures Recent developments make photonic interconnect look feasible, even as the feature sizes of integrated circuits move into the few tens of nanometer range A. Logical-to-Frequency Addressing • Electrically connected • The problem gets worse as the components shrink deep into the nanoscale (RC time) • Inducing currents in the adjacent wires • Optically connected • Multiplexer associates a unique frequency “fingerprint” with each subunit of RAM • Can operate without any specific information regarding the physical location of a particular subunit of RAM

14. Global photonic interconnect architectures • Architecture of a nanophotonic data transfer system for chip to chip • Off-chip multiwavelength laser source • On device electrooptic modulators and photodetectors • Architecture of a nanophotonic data transfer system for chip-to-RAM/sensor/logic communication • Modulated signal emerging from the chip can e split using 3-dB couplers

15. Global photonic interconnect architectures B. Data Transfer Among Tiles and Mosaics • Architecture of WDM nanophotonic interconnect components and their interfaces with mosaics of molecular RAM/logic • Virtual fibers are separately encoded and decoded by photodetectors and modulators

16. Components for local photonic interconnect A. Integrated Optoelectronic Components • Example of an RCE(resonant cavity enhanced) photodetector for demodulation of an encoded wavelength channel • Dimension is 100-150 nm  Intrinsic capacitance of the doped region is 2aF • Similar considerations can be applied to the design of a RCE modulator

17. Components for local photonic interconnect B. Plasmonic waveguides and couplers • In order to implement photonic data transfer, nanoscale low-power optical modulators are needed  Resonant cavity modulators • Two mechanisms for resonant modulators operating • A shift of the resonant peak away from the optical channel center • A change in the resonant cavity loss • The shift of a resonant cavity due to a change of the refractive index • : The shift in the original cavity resonant frequency • λ : The original center wavelength • Δn : The change in refractive index • n : The original cavity refractive index • Modulation depth M (defined as the on-off power ratio) • : The original signal bandwidth

18. Components for local photonic interconnect C. Candidate Modulator Designs • All-Silicon Modulator • Operate multigigabit data rates  Recombination lifetime in silicon • By implantation of fluorine ions, the recombination lifetime can be reduced, or • DC-biasing the modulator so any carriers generated will be quickly swept out of the modulator • Hybrid Silicon Modulators • In order to reach faster modulation speeds, consider materials other than silicon (ex. Lithium niobate) • Some polymers and inorganic crystals , InP & GaAs on the silicon • Active Layered Modulator • Involving fabricating a thin layer of III-V material directly onto the cavity structure

19. Components for local photonic interconnect D. Nanoscale Si Photodetectors • A Si-Ge MSM photonic-crystal-cavity-enhanced photodiode • Nanoscale photodiodes can be combined with resonant cavities to allow efficient detection at selected wavelengths

20. Nanophotonic waveguides and resonators for global interconnect • Photonic Crystal Waveguides and Resonators • Single defect PhC cavity  Approximately 3-4 um2 • Each complete transceiver would occupy 30-40 um2 • Challenges for use of PhC • - Optical loss  Surface roughness introduced during • the fabrication process • Experimentally, losses for PhC (6 dB/cm) are higher than the closest corresponding planar ridge waveguides(3 dB/cm)

21. Nanophotonic waveguides and resonators for global interconnect • B. Ridge Waveguides and Microresonator • Conventional ridge waveguide technology is very well known, with easier design, fabrication, and understanding than PhC • Microcavities based on ridge waveguides generally consist of either Fabry-perot cavities using Bragg reflection or whispering-gallery cavities • Considering an entire transceiver, the required area is about 200 um2 (a factor of about ten larger than that of the corresponding PhC) • The fabrication is less complex than PhC & losses are bout a factor of two lower

22. Nanophotonic waveguides and resonators for global interconnect C. Hybrid Three-Dimensional Architectures • An elegant way to mitigate the size difference between optical and electrical components is to employ a 3-D design, where the optical components reside on a different layer than nanoelectronic circuitry • Bottom layer contains nanoelectronic circuitry along with PhC-based photodetectors &modulators • These PDs and modulators are coupled to the ridge waveguide optical bus residing on a top layer

23. Conclusions • There are many challenges to implementing on-chip photonic global interconnect • Low loss & small area waveguide structures to efficiently transport photons • High-efficiency transceivers to exchange information between photons and electrons • Can be built using standard semiconductor fabrication procedures