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ASIC 120: Digital Systems and Standard-Cell ASIC Design. Tutorial 1: Introduction to Digital Circuits January 25, 2006. Outline. Digital Systems Digital Design and its relation to ASICs Combinational Logic NOT, AND, OR, XOR, NAND, etc. mux, half-adder, full-adder Sequential Logic

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## ASIC 120: Digital Systems and Standard-Cell ASIC Design

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**ASIC 120: Digital Systems and Standard-Cell ASIC Design**Tutorial 1: Introduction to Digital Circuits January 25, 2006**Outline**• Digital Systems • Digital Design and its relation to ASICs • Combinational Logic • NOT, AND, OR, XOR, NAND, etc. • mux, half-adder, full-adder • Sequential Logic • flip-flop/register, shift register, counter**Digital Systems**• Analog vs. Digital • continuously varying vs. discrete • imprecise vs. precise • 0..1 vs. 0 or 1 • Digital systems excel at… • repetitive calculations • large amounts of data • reproducible results**Digital Systems**• Implemented in integrated circuits (ICs) mounted on a printed circuit board (PCB)**Components of a Digital System**• Printed circuit board (PCB) • Embedded software • microprocessor • microcontroller • digital signal processor (DSP) • ASIC • Programmable Logic Device (PLD) • FPGA, etc.**ASICs**• Application Specific Integrated Circuit • from a user perspective, implies integrated circuit with a specific application • from a design perspective, implies any integrated circuit • Since we are designers, ASICs include • SRAMs • phase locked loops (PLLs) • microprocessors • analog-to-digital converters • FPGAs • etc.**Consider an ASIC**• Physically comprised of • Package • Pins • Silicon wafer • metal interconnect layers • insulating layers • vias • at the bottom, transistors resting on a silicon substrate**Consider an ASIC: Side View**Source: Figure 3-11 from ECE 438 textbook (Rabaey, Jan M., Anantha Chandrakasan, Borivoje Nikolić, “Digital Integrated Circuits: A Design Perspective,” 2nd Edition; Pearson Education: New Jersey, 2003.)**Consider an ASIC: Substrate**Source: Figure 3-13 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)**Consider an ASIC**• Conceptually • System • Module • Gate • Circuit • Device Source: Figure 1-6 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)**FPGAs**• Field Programmable Gate Array • part of the Complex Programmable Logic Device (CPLD) family of PLDs • essentially reprogrammable hardware • FPGAs can be very small or very big • clock rates over 1 GHz • implement multiple 32-bit processors**Components of an FPGA**• Logic Elements (LEs) • Routing • Input/Output logic • Extra features • clocking • memory • memory interfaces • multipliers**The Logic Element**• Two main parts • Look-Up Table (LUT) for combinational logic • Flip Flop (FF) for sequential logic (memory)**Digital ASIC/FPGA Design Flow**• Dependent on target environment, process, resources available, etc. • Generic flow: • System architecture • Register Transfer Level (RTL) • high level, synthesizable, optimized • functional simulation, timing simulation • Synthesis • more simulation • Manufacturing • testing**Register Transfer Level (RTL)**• This is where we start • schematic • hardware description languages (VHDL, etc.)**Combinational and Sequential Logic**• We can break a digital system into two types of logic • Combinational • computation happens in a linear fashion • Sequential • computation involves a feedback loop (memory)**RTL and Combinational/Sequential Logic**Sequential Feedback Data Out Data In Register Register Register Cloud of Logic Cloud of Logic Clock Combinational**Combinational Logic: NOT**Truth Table Input Output Boolean algebra expression: X = A**Combinational Logic: AND**Boolean algebra expressions: X = A B X = AB**Combinational Logic: OR**Boolean algebra expression: X = A + B**Combinational Logic: XOR**Boolean algebra expression: X = A B**Combinational Logic: NAND**Boolean algebra expressions: X = A B X = AB**NAND: Transistor Layout**vdd gnd**Combinational Logic: NOR, XNOR**X = A + B X = A B**Building Combinational Circuits**X = AC + BC**Combinational Logic: MUX(multiplexer)**X = AC + BC**Half Adder**S = A B C = AB**Full Adder**S = A B Ci Co = AB + Ci(A B)**A B**A B A B A B A B A B A B A B Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co S S S S S S S S Full Adder Application: 8-BitRipple-Carry Adder • Constructed by connecting 8 full adders together A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 0 Carry Out S0 S1 S2 S3 S4 S5 S6 S7**What I’ve Skipped**• Gates with more than two inputs • Karnaugh maps • Quine-McCluskey method • Binary arithmetic, base conversions • Practical digital circuits have more than 0s and 1s • Transmission gates, tri-state buffers**Simplified truth table:**Basic Feedback Element: SR Latch**Basic Feedback Element: SR Latch**0 0 1 0 (Hold State)**Basic Feedback Element: SR Latch**0 0 1 0 1 0 (Hold State)**Basic Feedback Element: SR Latch**0 1 0 0 (Hold State)**Basic Feedback Element: SR Latch**0 1 0 1 0 0 (Hold State)**Basic Feedback Element: SR Latch**0 0 1 1 (Set State)**Basic Feedback Element: SR Latch**0 0 1 0 1 1 (Set State)**Basic Feedback Element: SR Latch**0 0 1 0 0 1 (Set State)**Basic Feedback Element: SR Latch**0 0 0 0 0 1 (Set State)**Basic Feedback Element: SR Latch**0 1 0 0 0 1 (Set State)**Basic Feedback Element: SR Latch**0 1 0 1 0 1 (Set State)

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