ASIC 120: Digital Systems and Standard-Cell ASIC Design

1. ASIC 120: Digital Systems and Standard-Cell ASIC Design Tutorial 1: Introduction to Digital Circuits January 25, 2006

2. Outline • Digital Systems • Digital Design and its relation to ASICs • Combinational Logic • NOT, AND, OR, XOR, NAND, etc. • mux, half-adder, full-adder • Sequential Logic • flip-flop/register, shift register, counter

3. Digital Systems • Analog vs. Digital • continuously varying vs. discrete • imprecise vs. precise • 0..1 vs. 0 or 1 • Digital systems excel at… • repetitive calculations • large amounts of data • reproducible results

4. Digital Systems • Implemented in integrated circuits (ICs) mounted on a printed circuit board (PCB)

5. The Big Picture

6. The Big Picture

7. Components of a Digital System • Printed circuit board (PCB) • Embedded software • microprocessor • microcontroller • digital signal processor (DSP) • ASIC • Programmable Logic Device (PLD) • FPGA, etc.

8. ASICs • Application Specific Integrated Circuit • from a user perspective, implies integrated circuit with a specific application • from a design perspective, implies any integrated circuit • Since we are designers, ASICs include • SRAMs • phase locked loops (PLLs) • microprocessors • analog-to-digital converters • FPGAs • etc.

9. Consider an ASIC • Physically comprised of • Package • Pins • Silicon wafer • metal interconnect layers • insulating layers • vias • at the bottom, transistors resting on a silicon substrate

10. Consider an ASIC: Package

11. Consider an ASIC: Side View Source: Figure 3-11 from ECE 438 textbook (Rabaey, Jan M., Anantha Chandrakasan, Borivoje Nikolić, “Digital Integrated Circuits: A Design Perspective,” 2nd Edition; Pearson Education: New Jersey, 2003.)

12. Consider an ASIC: Substrate Source: Figure 3-13 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)

13. Consider an ASIC • Conceptually • System • Module • Gate • Circuit • Device Source: Figure 1-6 from ECE 438 textbook (Rabaey et al., “Digital Integrated Circuits,” 2nd Edition)

14. FPGAs • Field Programmable Gate Array • part of the Complex Programmable Logic Device (CPLD) family of PLDs • essentially reprogrammable hardware • FPGAs can be very small or very big • clock rates over 1 GHz • implement multiple 32-bit processors

15. Components of an FPGA • Logic Elements (LEs) • Routing • Input/Output logic • Extra features • clocking • memory • memory interfaces • multipliers

16. The Logic Element • Two main parts • Look-Up Table (LUT) for combinational logic • Flip Flop (FF) for sequential logic (memory)

17. Top Level View of an FPGA

18. Top Level View of an FPGA

19. Digital ASIC/FPGA Design Flow • Dependent on target environment, process, resources available, etc. • Generic flow: • System architecture • Register Transfer Level (RTL) • high level, synthesizable, optimized • functional simulation, timing simulation • Synthesis • more simulation • Manufacturing • testing

20. Register Transfer Level (RTL) • This is where we start • schematic • hardware description languages (VHDL, etc.)

21. Combinational and Sequential Logic • We can break a digital system into two types of logic • Combinational • computation happens in a linear fashion • Sequential • computation involves a feedback loop (memory)

22. RTL and Combinational/Sequential Logic Sequential Feedback Data Out Data In Register Register Register Cloud of Logic Cloud of Logic Clock Combinational

23. Combinational Logic: NOT Truth Table Input Output Boolean algebra expression: X = A

24. Combinational Logic: AND Boolean algebra expressions: X = A  B X = AB

25. Combinational Logic: OR Boolean algebra expression: X = A + B

26. Combinational Logic: XOR Boolean algebra expression: X = A  B

27. Combinational Logic: NAND Boolean algebra expressions: X = A  B X = AB

28. NAND: Transistor Schematic

29. NAND: Transistor Layout vdd gnd

30. Combinational Logic: NOR, XNOR X = A + B X = A  B

31. Building Combinational Circuits X = AC + BC

32. Combinational Logic: MUX(multiplexer) X = AC + BC

33. Half Adder S = A  B C = AB

34. Full Adder S = A  B  Ci Co = AB + Ci(A  B)

35. Full Adder

36. A B A B A B A B A B A B A B A B Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co Ci Co S S S S S S S S Full Adder Application: 8-BitRipple-Carry Adder • Constructed by connecting 8 full adders together A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7 0 Carry Out S0 S1 S2 S3 S4 S5 S6 S7

37. What I’ve Skipped • Gates with more than two inputs • Karnaugh maps • Quine-McCluskey method • Binary arithmetic, base conversions • Practical digital circuits have more than 0s and 1s • Transmission gates, tri-state buffers

38. Sequential Logic

39. Basic Feedback Element: SR Latch

40. Simplified truth table: Basic Feedback Element: SR Latch

41. Basic Feedback Element: SR Latch 0 0 1 0 (Hold State)

42. Basic Feedback Element: SR Latch 0 0 1 0 1 0 (Hold State)

43. Basic Feedback Element: SR Latch 0 1 0 0 (Hold State)

44. Basic Feedback Element: SR Latch 0 1 0 1 0 0 (Hold State)

45. Basic Feedback Element: SR Latch 0 0 1 1 (Set State)

46. Basic Feedback Element: SR Latch 0 0 1 0 1 1 (Set State)

47. Basic Feedback Element: SR Latch 0 0 1 0 0 1 (Set State)

48. Basic Feedback Element: SR Latch 0 0 0 0 0 1 (Set State)

49. Basic Feedback Element: SR Latch 0 1 0 0 0 1 (Set State)

50. Basic Feedback Element: SR Latch 0 1 0 1 0 1 (Set State)