Development of a programmable clock distribution ASIC for LHCb calorimeters

1. Development of a programmable clock distribution ASIC for LHCb calorimeters Why did we develop this ASIC ? Chip requirements Channel architecture Simulation results First test bench results Journées VLSI IN2P3 - 11 juin 2002

2. Calorimeter front-end electronics Overview of the front-end elements Digital Analog Block diagram of the front-end board Delay chip

3. Implications of the LHCb specific requirements for the F.E electronics • On the front-end boards of the calorimeter electronics, we need to adjust the 40MHz clock for each of the 32 12-bit ADCs. • This clock has to be transmitted over low level differential lines • The current solutions are : • clock distribution COTS ( like CY7B991 from Cypress) + LVDS or PECL translators • CMS’s (a.k.a Marchioro’s) Delay Chip + the same translators • The inherent problem at the electronics location is the SEU hardness and the mandatory readback access to the configuration data • The board occupancy and the total cost also have to be taken into account • Those elements lead us to study this new possibility ...

4. + Clk out 0 - + Clk out 1 - + Clk in - + Clk out 2 - + Clk out 3 - I2C SDA SCL New ASIC requirements • The new ASIC has : • to be able to deal with unipolar or differential inputs and outputs • to integrate 4 clock channels • to cover the 25ns range with independent steps of 1ns on each channel • to have the smallest possible dependence on temperature and on output load • to be insensitive to SEUs in its configuration part • to be loadable and back readable by I2C • to use a small but easy to use package • to work under 3.3V => We designed a new phase comparator, with no dead area, no phase noise and no sensitivity to the technology corners. =>The outputs are servo-controlled.

5. Block diagram of the new ASIC Phase comp + Charge pump + CLK 25ns delay line - CLK Select delay from I2C Phase comp + Charge pump 25 -> 1 mux 7ns delay line + delay line CLK out - Phase comp + Charge pump delay line

6. Channel layout Input buffer Servo 1 Main DLL Positive output buffers Servo 2 MUX Servo 3 Negative output buffers Decoder

7. DLL convergence and output signals Output signals in pseudo LVDS mode Negative output DLL (servo 3) Positive output DLL (servo 2) Main DLL (servo 1)

8. Waves on test bench. Diff out Clk in Out + Out -

9. How to make pseudo LVDS with 3.3V CMOS complementary outputs 330 ohms SIG 1.65V DC offset 400mV differential 3.3V CMOS 100 ohms 330 ohms SIG

10. Conclusion • After having studied both the requirements and the implementation and costs implications, we decided to launch the design of a new clock distribution chip • Its main features are the following : • 4 channels with adjustable steps of 1ns over 25ns • time-locked outputs • mixable unipolar or differential I/Os • built in SEU hardness and readback access • The serial interface is I2C and the package PLCC-28. • The first 2-channel prototype launched in 0.8u CMOS from AMS is functional and has to be thoroughly characterized. Nevertheless, the first measurements show a good time linearity and a very low jitter (<30ps RMS). • Irradiation in a proton beam is also foreseen to check the SEU hardness.