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Development of new ASIC

Development of new ASIC. 1. New pilot ASIC progress report 2. GOL test 3. Development of new pilot module. Hiroyuki Kano RIKEN. New ASIC was submitted. The new ASIC was submitted at the end of May. 6x8mm chip size IBM 0.25 m m process with radhard cell library (same as ALICE pilot)

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Development of new ASIC

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  1. Development of new ASIC 1. New pilot ASIC progress report 2. GOL test 3. Development of new pilot module Hiroyuki Kano RIKEN

  2. New ASIC was submitted The new ASIC was submitted at the end of May. • 6x8mm chip size • IBM 0.25mm process with radhard cell library (same as ALICE pilot) • CERN Multi Project Wafer (same as ALICE pilot) • Additional 32bit input and 16bit output

  3. Pilot module 32 256 What is New ASIC • ALICE chip is 32bit input/40MHz x 16bit output • New chip is 64bit input/40MHz x 32bit output 4x parallel readout

  4. 40MHz 10MHz 32bit 32bit x4 10MHz 16bit x4 40MHz Pixel data B31 - B16 Pixel data B15 - B0 Event number 16bit Fast or 31 – 16 bit JTAG return - 40MHz x 16 = 0.64Gbps 40MHz x 32 = 1.28Gbps Output format frame0 frame1a frame1b 10MHz 16bit x4 40MHz slot0 slot1 slot2 slot3 slot2 slot3 16bit Event number Pixel data A31 - A16 Pixel data A15 - A0 15 – 0 bit Fast or JTAG return - 10MHz Idle start readout readout

  5. RIKEN-pilot2004 mask image The large chip size (6x8mm) for additional I/O pins (ALICE original : 6x4mm) 184 I/O pins (32x2 input and 16x2 output) Submitted at the end of May Will be delivered in this September (80 chips) This is a straight-forward modification, and it is very likely that it work for the first trial. Any small bug in the first version can be fixed in the next submission in Dec.

  6. GOL (32bit mode) • GOL has 32bit data transfer mode (1.6Gbps) • We will start checking err rate for this mode soon, and will finish at the end of July. Test set up (plan) GOL TLK2501 FPGA 32bit mode Texas Instruments 32bit to serialized data Serialized data to 16bit (80MHz) 16bit (80MHz) to 32bit (40MHz) check

  7. data G OE/EO 64b data data data data data data data data data data G G G G G OE/EO OE/EO OE/EO OE/EO OE/EO CLK ctrl 32b 32b 32b 32b 32b data CLK CLK CLK CLK CLK G OE/EO A A A A A 64b ctrl ctrl ctrl ctrl ctrl bus bus bus bus bus opt opt opt opt opt CLK A ctrl 1.6Gbpsmode bus opt New pilot module d.pilot d.pilot d.pilot d.pilot d.pilot d.pilot d.pilot New pilot module plan The original pilot module What are changes: Additional 4 bus inputs, GOL, and OE/EO

  8. Schedule • New chips will be delivered in this September. • I start checking the 32bit operation of GOL. • I start development of the test board and prototype pilot module for new chip. September Jun GOL test New chip delivered New ASIC was submitted New pilot module board design Chip test New pilot module test

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