Reducing Synchronization Overhead in Test Data Compression Environments

1. Reducing Synchronization Overhead in Test Data Compression Environments Nicola Nicolici Electrical and Computer Engineering Paul Theo Gonciari Bashir Al-Hashimi Electronic Systems Design Group University of Southampton, UK McMaster University, Canada

2. Overview • TDCE and synchronization issues • Generic on-chip decoder • Synchronization overhead in TDCE • Previous solutions • Tailoring the compression method • Interleaving architecture • Proposed solutions • Tailoring the compressed test set • Distribution architecture • Experimental results • Conclusions

3. Test data compression • Exponential increase in volume of test data (ITRS) • 60% of ATE upgrade caused by memory (EETimes) • Solutions Built-in self-test (BIST) Test data reduction • Useless – UMA [Gonciari et. al, VTS02] • Useful – test data compression • TDCE [Gonciari et. al, DATE02] uncompressed ATE compressed On-Chip Decoder CUT SOC

4. Serial decoder PG and CI can not work independently Implicit communication between PG and CI Parallel decoder PG and CI can work independently Explicit communication between PG and CI Generic on-chip decoder

5. Synchronization overhead - Serial decoder • De-serialization unit • Multiple ATE channels and FIFO-like structure • Synchronization channels necessary

6. Synchronization overhead - Parallel decoder • NO De-serialization unit • Single ATE channel and FIFO-like structure • Synchronization channels necessary

7. Previous solution – Serial decoder • Interleaving architecture [Chandra et. al, TCAD01] • Single channel FIFO-like structure • Synchronization channels • Interleaving FSM • Changes serial-decoders to ease the control • Does not exploit frequency ratio

8. Previous solution – Parallel decoder • Tailoring the compression method [Jas et. al, VTS99] • Decoderdependent on frequency ratio • Imposes ATE restrictions • Changes the on-chip decoder • NOFIFO-like structure needed • NO interleaving FSM

9. Proposed core level solution • Tailoring the compressed test set • Applicable when FIFO-like structures are needed • Insert dummy bits • FIFO-like structure is eliminated • NO changes to on-chip decoders • Decoder independent of the frequency ratio tcmp= 000 001 1stop1stop1 011 1 010 t’cmp= 000 001 1D 1D 1 011 1 010

10. SOC Proposed system level solution Distribution architecture

11. Composite test set Tailor compressed test sets Simple merge procedure Distribution architecture • NO changes to on-chip decoders • Easy design integration for TDC system test • Applicable to any parallel decoder • Applicable to LFSR architectures when reseeding • IEEE 1149.1 compatible solution for SOC TDC test • Reduces trade-off

12. cmp vs. set – s38417(a = 2)

13. cmp vs. set – s38417 (a = 4)

14. cmp vs. set vs. distr – S1

15. inter vs. distr – S2

16. Conclusions • Synchronization overhead in TDCE • Proposed two solutions • Core level solution • Tailor the compressed test set • System level solution • Distribution architecture • IEEE 1149.1 compatible solution for SOC TDC test • Future work • Integrate TDC in system level design flow

17. Example – VIHC [Gonciari DATE02] • Core level solution tcmp= 000 001 1stop1stop1 011 1 010 t’cmp= 000 001 1D 1D 1 011 1 010