VDSM and Full-Custom Layout Design Issues(1)

1. VDSM and Full-Custom Layout Design Issues(1)

2. Contents • Technology and Foundry Mega-Trend • VDSM (Very Deep Sub-Micron) Issues • Full Custom vs. Standard Cell Layout

3. Technology and Foundry Mega-Trend

4. Foundry Scene • Leading-edge platform • 0.09 and 0.065 micron • Copper interconnect, True low-K dielectric • Rich library and IP; • Mixed Mode and RF • Embedded DRAM, SRAM • High-Speed I/O • Solution and Service Oriented Environment • Library, IP, EDA tool, and Design Kit • Back-end, testing, packaging support • Cost-effective manufacturing • Long-term Partnership

5. Foundry Scene • Top 10 Semiconductor manufacturers • Intel ($ 30 B) • Samsung ($20 B) • TI • Infineon • Renesas • ST Micro • Toshiba • TSMC • NEC • Philips • Hynix (~8?)

6. VDSM (Very Deep Sub-Micron) Issues

7. Technical Issues in DSM design • Manufacturability (Chips can’t be built!) • Antenna rules • Density rules • Minimum area rules for stacked vias • CMP(Chemical mechanical polishing) area fill rules • Layout correction for optical proximity effects in sub-wavelength lithography • Signal Integrity (Failure to meet functional/timing targets.) • Crosstalk/noise-induced errors • IR drop on power supply • Reliability (design failures in the field) • Electro-migration on power supply rails • Hot electron effect on devices • Wire self-heat effect on clock and signals

8. Abstraction Accuracy SOC / DSM Design Dilemma • DSM • Higher resistance • Higher cross-coupling • Non-linear timing • IR drop • Electromigration • Inductance • SOC • Time-to-market • Larger die, larger database • Bigger design space • Longer wires, higher density • Higher clock speeds • Reuse, IP’s Requires detailedanalysis to properly incorporate relevant physical interactions Requires higher abstraction levels to manage the complexity

9. aggressor 1 D Q 0 clock reset victim Setup violation due to aggressor D Q victim clock reset aggressor Signal Integrity: Noise/Crosstalk Impact on Digital Designs • Symptom • Chip fails repeatedly on certain logic operations. • Functional failures • When the noise or crosstalk is coupled to a static signal. • Timing failures • when it is coupled to a switching signal. Reference: CeltIC, CadMos

10. Clock Tree Generation • Clock wire self heat prevention • Clock hot electron prevention Placement Optimization • Crosstalk prevention • Signal wire self heat prevention • Signal hot electron prevention • Concurrent analysis and prevention • Automatic prevention and correction • Global view while fixing problems • Eliminates over-design Power Analysis • Voltage drop analysis • Electromigration analysis Detail Routing • Crosstalk fixing • Shielded routing • Wide space routing RC Extraction • Cross-coupling parasitics Timing Analysis • Crosstalk delay analysis • Crosstalk glitch analysis Integrated Solution for Signal Integrity (SI) Issues Integrated SI prevention and correction

11. M3 M2 V1 M1 MC Poly What are to be solved? Dummy fills and metal slotting for uniform metal density, which, in turn, yields uniform IMD thickness Layout In Real Process, M2 CVD effect IMD1 CMP dishing effect M1 Loading in etching Optical proximity effect Process effects characterization RCL Extraction for Global and Local nets Vertical Tech. info. In Simulation, M2 Extraction IMD1 Exact solution Field solving M1 Ideal Manhattan structure

12. Spice Modeling IR Drop ElectroMigration Hot Carrier Effect OPC VDD GND Parasitic RLC EMI Coupling Noise Transmission Line High Freq. Effect I/O Process Variation Digital Delay & Power Analog Temperature ESD / Latch-up Substrate Noise Substrate Coupling Emerging Design Quality Issues Board SoC Package Reference: H. Yonezawa - ISQED 2000 Tutorial 1.2

13. Logic Synthesis Floorplanning Physical Synthesis Power Routing Detail Routing Signal Integrity Chip Assembly Clk Tree Syn. Place and Route Common Static Timing Analysis Route Area Topology SI Clock Place Area Area Power Topology Timing Timing Cell Timing Design Becomes More Interdependent Floorplanning Physical Synthesis Clk Tree Syn Clk Tree Syn. Power route Power route Detail Routing Detail Routing Chip Assembly Chip Assembly • 0.25 mm • 300K Gate Conventional Synthesis & P&R • 0.18 mm • 3M Gate Physical Synthesis, Optimization P&R

14. Physical Synthesis • Motivation: DSM timing closure is unpredictable. • Poor correlation between synthesis and P&R timing. • Repair methods are too slow to converge. • Physical Synthesis • Physically accurate timing in synthesis • Eliminates iteration • Produces higher performance designs Root Problem Synthesis Timing Inaccuracy Performance Physical Synthesis P&R 600MHz 550MHz Synthesis Post Placement Synthesis IPO 500MHz P&R P&R Design stages

15. RTL/Gate Source Timing Constraints Physical Constraints Physical Synthesis Parsing, Structuring, Mapping DFT Scan Chain Insertion Initial Floorplan/Auto Block Place Pre-Placement Optimization Initial Placement Scan Chain Reorder Common Timing Engine Clock Tree Synthesis Optimization Transforms restructure, clone, remap, buffer, etc Synthesis Library Incremental Placement 106 Incremental Route & Incremental Time using fast router accept /reject Physical Library Timing Driven Global Routing RC reduce/Delay Calc Algorithms {Post-Final Route Incremental Optimization} Netlist Timing Constraints Final and Legal Placement Global Routing Database SPEF D/RSPF optimization place-and-route Final Route RC Extract A Physical Synthesis Solution • Floorplanning Capabilities • Cell/Block Placement • Global route correlation (deviation within 3%) • Powerful Logical Optimizations • Physical Power Planning • Clock Tree Synthesis • Scan Chain Reorder • Low Power Optimization • Datapath Synthesis • Sign-off Quality Timing • >Million Gate Capacity

16. Full Custom vs.Standard Cell Layout

17. Design Style • Cell-based design • Synthesis and P&R • CAD tools well available • High productivity, Time-to-market • Full custom design • Transistor Sizing • High-performance • Floorplan

18. Cell-based P&R • Chip planning • Hierarchical floorplan, mixed hard-soft block placement • Routing planning of all global nets (control/data signals, clock, P/G) • Induces pin assignment/ordering, hard(partial) pre-routes • Individual block design – various P&R methodologies • Chip assembly • Early Floorplan : estimated RC with quick placement • power grid/ring/strip/mesh • quick power analysis : static at first, dynamic later

19. Why Full Custom Design? • Exploit flexibility of transistor level layout • Analog circuits (tune for noise, gain, etc) • High-performance design (highest speed, lowest power) • Ex. 4x speed, 1/3 area, 1/10 power • Low cost mass production (smallest die) • IP differentiation • New approach • Technology migration – Hard IP optimization (DSM issues + area + performance), compaction • Transistor level layout synthesis – fine tuned • Datapath, cell mixed layout compiler - productivity

20. Full Custom Design • Circuit Design • Start from Micro-architecture • RTL logic restructuring, repartition (custom design vs. standard cell) • Floorplan -- area budgeting • Interface timing budgeting – Gantt chart • Circuit style & Transistor Sizing • Dynamic, Cross-coupled logic, static, self-timed. • Layout Implementation • Circuit design review • Layout package • Micro floorplan : approximate location of sub block • detailed layout style, Interconnect plan • Estimated block size • power/clock/signal distribution • Time-critical bus plan

21. Design Review • Objective • catch potential problem at an early design stage before the next phase is started • Incipient Design Review • Identify preliminary timing, power, area estimation, floorplan • Pre-layout Design Review • setup/hold, noise margin, cross-coupling, leakage, power, hot election( signal slope ), bus keeper, clock balancing • Complete Floorplan with signal, clock and power routing • Layout package • Final Design Review • Post layout Static timing, simulation • Complete final timing chart, power consumption • Layout Plot check -- rubber band in Metal or poly -- sufficient power strap and via, clock routing • Critical signal labeling for Ebeam probing • EM and IR drop, Antenna rule • un-contacted long poly, long TR finger • ECO

22. PLL I-cache D-cache TAG Branch History system Load/ Store TLB Fetch Media Pipe Control Unified Integer FPU MEDIA/ MAC Control MAC RF Early Chip Footprint Final footprint Early plan Continuous Plug-in

23. Full custom design message • Floorplan; 설계의 결과가 아니라, 설계의 견인차이다. • Floorplanning with Interconnect in mind is the only way in DSM design • Core of the FP is ‘ambiguity management’ through area, timing, power budgeting • 270mm2 chip이 P&R로 70mm2가 되지는 않는다 • 10MHz설계가 TR size바꾼다고 50MHz로 동작하지 않는다 • 기존의 설계 결과를 분석해서 정량적인 데이터를 얻음 • Web-based design management system • Task submission/approval/assignment/announcement for critical path reporting, bug reporting/tracking, ECO, etc. all thru. consistent design management system.

24. Floorplan-based ASIC Layout • Objective • Reducing turn-around-time w/o expensive iteration • Early pinpointing the physical design issue at architecture define stage and early feedback • Floorplan-based power and clock distribution • Determining time-critical buffer sizing and Bus/Interconnect planning • Early timing closure • Early attention to deep submicron physical issues and signal integrity

25. 5 Million Gates Example Final footprint Early plan Continuous Plug-in