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GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL

GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL. PROMETEO workshop. November 17-18 2011, Valencia. Outlines. NEDA . Global Trigger and Synchronization Firmware Optical Gigabit Link (LINCO) Expected Activities. TRACE. FEE options Reduced output

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GTS, Optical Link and TRACE Front End Electronics Andrea Triossi INFN - LNL

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  1. GTS, Optical Link andTRACE Front End ElectronicsAndrea TriossiINFN - LNL PROMETEO workshop November 17-18 2011, Valencia

  2. Outlines NEDA • Global Trigger and Synchronization Firmware • Optical Gigabit Link (LINCO) • Expected Activities TRACE • FEE options • Reduced output • Sparse readout • RO and Trigger on FPGA • Expected Activities

  3. GTS: Functionalities • Common clock • Global clock counter • Global event counter • Trigger requests • Error reports • Trigger controls: • Throttling of the L1 validation signal • Fast commands (fast reset, initialization, etc.) • Fast monitoring feedback from the crystals • Calibration and test trigger sequence commands • Monitor of dead time MGT Local Tag Generator Trigger Request TX Local Tag Uplink RX Trigger Match Valid / Reject MEM Val/Rej Tag

  4. GTS: CurrentLimits • Serves just one trigger request Interface for 16 • Handles just one ID request 16 ID per GTS core • Single communication interface Split into two? one towards V6 and one inside V5

  5. GTS Interfaces • Trigger Requests • GTS Services 22 lines (request, validation/rejection) + 16 due to requester ID (concurrent trigger requests) = 38 lines between V5 and V6 Linux VxWorks • PPC running • Hardware implemented ?

  6. What is LINCO? Adapter to translate PCI Express signals to/from the optical physical layer suitable for legacy bus standards (PCI, cPCI, VME…) local bus remote bus • Already adopted by several experiments: • AGATA (moving from V1 to V2) • CMS @ CERN (since 2005 in harshenvironmental conditions) • ICARUS • WARP @ LNGS

  7. LINCOFlavors x1 PCIEx PCI 1 REF CLK bus x1 PCIExx1 PCIEx 1 REF CLK bus • Clock issues • Spread Spectrum Clock • Clock out of spec 1x4 PCIEx / 2x2 PCIEx / 4x1 PCIEx Motherboard/Oscillator REF CLK x4 PCIEx bus PCIEx Switch GEN2 20 Gb/s aggregate

  8. LINCOV2

  9. PCI-Ex DMA Transfer PCI-Ex Endpoint RAM PCI-Ex Endpoint PCI-Ex Endpoint CPU Root Complex PCI-Ex Endpoint PCI-Ex Endpoint DMA engine continuously write on PC RAM holding the processor bus. If we want to run concurrently online trigger algorithms or even analysis programs that access the main memory, the DMA transfer will be stopped The higher the throughput the bigger the buffering

  10. Expected Activities Global Trigger and Synchronization • New Firmware • Test bench on a small tree (GTS mezzanine?) • Test on a Numexo carrier LINCO • x2 (x4) PCI Express core deployment • Communication test LINCO-Numexocarrier • Check compatibility issues between LINCO and PC farm

  11. TRACEFEE Requirements TRACE ASIC • Spherical chamber Ø 26cm • 10K channels • PA inside the chamber Integrated PA Analog Memory for multiplexing Technology • CMOS 180 nm • Low consumption (1-10 mW) • Fast switching • High integration

  12. TRACE FEE Requirements Consumption • Digitizer out of the chamber • PA 2 mW/ch 200 mW/ASIC 20 W/array • (~the same from the analog memory) Throughput • Rising time: 20-200 ns • Bandwidth: 0.35/20 ns = 17.5 MHz • Sampling rate: 200 MHz • Rising time 200 ns, 200 MHz sampling rate: 40 samples • (2B each, 12bit ENOB) • 128 ch per ASIC • Rate/ch 100 Hz • Throughput: 1MB/s per ASIC (~80)

  13. PSA Feasibility Pre Amplifier • Transient signal: 1/10 net charge (from simulation) • Worst case: 5 MeV Alpha 50 mV • Gain: 10 mV/MeV (which Ion set the gain? Li?) • Bandwidth: 100MHz • ENC 10e rms • Dynamics: 150 MeV on 1.5 V

  14. A Trigger 200 MHz Comp Reduced Output . . . . . . . . . . . . . . . . . . . . M U X Input channels Q Amp Shaper 128x128 Memory cells B Encoder Controller Lookup Table 200 MHz Comp Sparse Readout . . . . . . . . . . . . . . . . . . . . M U X Input channels 128x128 Memory cells Q Amp Shaper

  15. C Trigger 200 MHz High speed Serial link . . . . . . . . . . A D C F P G A Input channels V/I Amp Memory cells 128x128

  16. FPGA as ADC FPGA V/I AMP TDC • From PA directly to FPGA differential inputs • External DAC used to produce a VREF linear ramp • TDCs measure time differences further converted to voltage V/I AMP TDC V/I AMP TDC V/I AMP TDC D A C V1 V2 V3 V4 Highest integration? T1 T2 T3 T4

  17. Dead Time Solution A • MUX switching time: typ. ~ 50 ns • Sampling Rate 200 MS/s per ch • Samples: 40 signal + 20 baseline • Memory depth: 128 samples • Dead time per ch: 50 ns + 128x5 ns = 640 ns • Dead time per ASIC: 128x350 ns ≈ 80 µs • 80 µs ~12 KHz (Elastic Scattering) • Simultaneous Read/Write ? • ROI Read out (60 samples) ?

  18. Prototype channel S. Ritt (PSI) • Analog memory (DRS4): 5 GS/s, 1024 cells, 9 ch (4 in the EVB) • ADC (AD9245): 14 bit, 80 MS/s • FPGA Xilinx Spartan3 • Microcontroller (CY2C68013A ) with USB connection

  19. Conclusions NEDA • Development of a New GTS Firmware • Test on NUMEXO carrier • Compatibility among PC-LINCO-NUMEXO TRACE • PA ASIC development • Analog memory prototype channel • TDC feasibility study • Global Trigger and DAQ: Compatibility Issues

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