1 / 25

Sensitization Criterion for Threshold Logic Circuits and its Applications

Author: 1 Chen-Kuan Tsai, 1 Chun-Yao Wang, 1 Ching-Yi Huang , 2 Yung-Chih Chen 1 National Tsing Hua University, Taiwan 2 Y uan Ze University, Taiwan Date: 2013/11/18. Sensitization Criterion for Threshold Logic Circuits and its Applications. Outline. Introduction Motivation

iliana-herring
Télécharger la présentation

Sensitization Criterion for Threshold Logic Circuits and its Applications

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Author: 1Chen-Kuan Tsai, 1Chun-Yao Wang, 1Ching-Yi Huang, 2Yung-Chih Chen 1National Tsing Hua University, Taiwan 2Yuan Ze University, Taiwan Date:2013/11/18 Sensitization Criterion for Threshold Logic Circuits and its Applications

  2. Outline • Introduction • Motivation • Problem Formulation • Sensitization Criterion for Threshold Logic • Types of Threshold Logic Gates (LTGs) • Sensitization conditions • Threshold Logic-based STA flow • Experimental Results • Conclusion and Future Work

  3. Threshold Logic • A threshold logic function f is a multiple input function defined as follows: f = 1 if 0if n binary inputs x1, x2, … ,xn with weights w1, w2, … ,wn a single binary output y, and a threshold value T • A linear threshold logic gate (LTG) is a multiple terminal device which implements a threshold function, and it can be represented as a weight-threshold vector < w1, w2, … ,wn ; T > • A threshold logic network is a network composed of LTGs … … … x1 x2 Xn-1 Xn w1 w2 wn-1 wn T f

  4. Threshold Logic • An example of <1, 1, 2; 2> f = 1 if 0if x1 x2 x3 x1 x2 f 2 1 1 2 f x3 Threshold logic gate

  5. Features of Threshold Logic • Not every Boolean function can be realized by a single LTG,e.g., the binate Boolean function • A threshold logic function must represent aunate Boolean function, but not every unateBoolean function can be synthesized as a single LTG, e.g., • Every Boolean function has infinitely distinct representations in the form of threshold logic, e.g., f=<1, 1, 2; 2>=<2, 3, 5; 5>

  6. Features of Threshold Logic • In theory, every Boolean function can be realized as a compact threshold logic network, which can result in fewer nodes and a shorter network depth 5 nodes and 3 levels 6 nodes and 4 levels

  7. Sensitization Criteria in Boolean Logic • Static sensitization criterion [1] • A path is static sensitizable path when all the side-inputs of the path hold non-controlling values • May underestimate the delay, though, can be used to estimate a lower bound of the actual delay • Exact sensitization criterion [2] • When the on-input holds a controlling value, the earlier arrived side-inputs must hold non-controlling values • When the on-input is the latest arrived input holding a non-controlling value, all its side-inputs must hold a non-controlling value as well [1] J. Benkoski, E. Vanden Meersch, L.J.M. Claesen, H. De Man, “Timing Verification Using Statically Sensitizable Paths,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 10723-10784, Oct. 1990. [2]H.-C. Chen and D. H.-C. Du, “Path Sensitization in Critical Path Problem,” IEEE Trans. Computer-Aided Design of Integrated Circuits and Systems, pp. 196-207, Feb. 1993.

  8. Motivation Possible approaches • Re-synthesize the LTG into a similar Boolean network and identify the input assignment for the path sensitization • Underestimated the result due to the lack of delay computation for LTGs • Unable to analyze the timing completely • Construct a threshold logic network only composed of primitive gates (AND, OR, …) such that the input assignment can be obtained easily • Inaccurate analyzed result due to the changed network structure 0 0 1 0 – 1 X1 X4 X3 X5 X6 X2 5 5 2 3 1 1 f 5 e.g., assume the target on-input is X5 and the arrival order is X1 > X2 > X3 > X4 > X5 = X6 0 0 0 0 X1 X4 X3 X5 X6 X2 f 1 0 1 (– represents ‘Don’t Care’)

  9. Problem Formulation • Given a threshold logic network, the corresponding delay model, a delay constraint D, and the upper bound of critical path quantity K • Objective: • To report at most K critical paths whose path delays are larger than D • The threshold logic network is synthesized by an ILP-based synthesis tool TELS [3] • Assume that the weights of every LTG are positive, and this assumption can be achieved by the negative-positive weight transformation [3] R. Zhang, P. Gupta, L. Zhong, and N. K. Jha, “Synthesis and Optimization of Threshold Logic Networks with Application to Nanotechnologies,” in Proc. Design Automation Test in Europe, 2004, pp. 904-909.

  10. Output Stability under Floating Mode • Condition 1: once the summation of stabilized-at-1s’ weights is greater than or equal to the threshold value, e.g., when x4 is stabilized at 1, the LTG outputs 1 • Condition 2: once the summation of stabilized-at-1s’ weights and remaining weights is less than the threshold value, e.g., when x3 is stabilized at 0, the LTG outputs 0 since w2+w4<5 x1 x2 x3 x4 x1 x2 x3 x4 f f 5 5 2 2 2 1 2 2 2 1 1 0 1 X->1 0 1 X->0 X assume LTG = {2, 2, 2, 1; 5} and the arrival order is x1 > x2 > x3 > x4 X->1 X->0 (X represents ‘Unknown’.)

  11. Dominant Input A dominant inputxi of an LTG exists if and only if the input satisfies either one of the following two equations where xiis stabilized at 1, xj is input arrives not later than xi and or where xi is stabilized at 0, xj is the input arrives not later than xi, xk is the later input than xi, and n is the number of inputs x1 x2 x3 x4 x1 x2 x3 x4 f f 5 5 2 2 2 1 2 2 2 1 1 0 X->1 X->1 0 1 X->0 X->0 X->1 X->0

  12. Terminologies for Input Grouping • Terminologies • A useless LTG outputs zero for all input combinations • A critical input of an LTG exists if the LTG becomes useless after removing the inputand its corresponding weight • A single-input group of an LTG is composed of a single input having the weight greater than or equal to the threshold value • A multiple-input group of an LTG is composed of inputs having smaller weights than the threshold value • An LTG having several groups is called a multiple-group LTG, otherwise, the LTG is called a single-group LTG

  13. Input Grouping f1 G1 • Input grouping is the process that separates the inputs and their corresponding weights of an LTG into different groups x3 x4 x5 x6 G2 For example, G1 is a single-group LTG, and both inputs X1, X2 are critical inputs to G1. G2 is a multiple-group LTG. 5 2 3 1 1 f 5 2 x1 x2 1 1

  14. Types of Threshold Logic Gates Type-1:Multiple-group LTG, given all of its groups are single-input groups Type-2:Single multiple-input group LTG, given all of its inputs are critical Type-3:Single multiple-input group LTG, given one or more of its inputs are not critical Type-4:Multiple-group LTG, given one of its groups is a multiple-input group x1 x2 x3 x1 x2 x3 x1 x2 x3 x1 x2 x3 f f f f 1 3 3 3 1 1 1 2 1 1 1 1 1 3 1 2

  15. The Proposed Sensitization Conditions • For Type-1 and Type-2 LTGs, apply the conventional exact sensitization criterion because of their identical functionality to Boolean OR/AND functions • For Type-3 and Type-4 LTGs, the on-inputs must be the dominant inputs of the LTGs in order to be sensitized • We construct a sensitization Binary-Decision Diagram (BDD) to derive the sensitization assignment

  16. Sensitization BDD a b c d a 0/4 wp / wn = 0/7 4 Then-edge (1) Else-edge (0) 3 2 1 1 3/7 b b f 0/2 2/4 3/5 5/7 c c 4/5 3/4 2/3 3/4 Assume the arrival order is a>b>c>d, and the on-input is c Sensitization conditions: (a, b, c, d)=(1,0,1,–) or (0,1,0,–) 1 0 (– represents ‘Don’t Care’.)

  17. Threshold Logic-based STA • Gate delay model: a normalized delay model, 1+0.35*(the number of fanins)from[5] • The wire delay is assumed to be 0. • Preprocess • Positive-Negative weight transformation • Input grouping • LTGs classification • Arrival time and required time computation • Violated paths enumeration • Path sensitization • Input assignment identification for satisfying the sensitization conditions of each on-input along aviolated path • This procedure is stopped until meeting one of the following requirements • 1. The number of critical paths is enough to report • 2. No more violated paths need to be examined [5]P. Celinski, S. Al-Sarawi, and D. Abbott, “Delay Analysis of Neuron-MOS and Capacitive Threshold-Logic,” in Proc. Int. Conf. Electronics, Circuits and Systems, pp. 932-935, 2000.

  18. Sensitization Conditions • For Type-1 or Type-2 LTGs Case 1: • If the on-input is one of the earliest input, the on-input is assigned to the controlling value Case 2: • If the on-input is one of the latest input, the on-input can be assigned to either the controlling value or the non-controlling value while the side-input must be assigned to the non-controlling value Case 3: • Otherwise, the on-input must be assigned to the controlling value, and those earlier side-inputs need to be assigned to the non-controlling value • For Type-3 and Type-4 LTGs • Construct a sensitization BDD to identify input assignments

  19. Start Path Sensitization (for each path Pj in the path list) The Overall STA Flow Input: A threshold logic network N, a delay constraint D, and a path number constraint K Sensitize xi on Gi+1 Preprocess Forward simulate Transform weight Is Gi+1 a PO? Group inputs Any conflict? No Yes Gi+1←Gi+2; xi←xi+1 Classify LTGs No Backtrack Mark Pj True/False Calculate required & arrival time Yes Collect violated paths Any other decisions? Yes Justify AlreadyKtrue paths? No No Yes End Output: Reporttrue paths and their delays

  20. Experimental Results • Implementation & platform • C Language, 3.0 GHz Linux platform (CentOS4.6) • The benchmarks • MCNC and IWLS2005 benchmark • These benchmarks were first synthesized into threshold logic networks with a default fanin number constraint, 6, which is the maximal number of inputs allowed in an LTG of the network • To demonstrate the accuracy of the proposed sensitization criterion and algorithm, we compared our results against the delays obtained from a timing simulation approach, which is an extension of the simulator provided in the synthesis tools TELS

  21. Table I • The experimental results of timing analysis for our approach and the exhaustive simulation approach using the delay model (1 + 0.35 × fanin) for K = 1 and K = 10

  22. Table II • The experimental results of timing analysis for our approach and the random simulation approach using the delay model (1 + 0.35 × fanin) for K = 1 and K = 10

  23. Table III • The experimental results of timing analysis for our approach and the exhaustive simulation approach using the delay model (1 + 0.35 × fanin + fanout)

  24. Conclusion and Future Work • We investigate and analyze different types of LTGs, and proposes the first sensitization criterion for threshold logic circuits. We also develops the first STA algorithm for threshold logic circuits • According to the experimental results, the proposed sensitization criterion correctly analyzed the delay for threshold logic circuits • However, the efficiency of the developed STA algorithm remains room for improvement • Future works include the development of efficient STA algorithms for threshold logic circuits and the studies of complex delay models, and further detailed timing optimization approach can be discussed

  25. Thanks for your listening.

More Related