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On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits. Department of Electrical and Computer Engineering. By Han Lin Jiun-Yi Lin. Overview. Introduction Principle and background Proposed reliability monitor circuit Circuit Blocks and Simulation Result :

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On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits

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  1. On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits Department of Electrical and Computer Engineering By Han Lin Jiun-Yi Lin

  2. Overview • Introduction • Principle and background • Proposed reliability monitor circuit • Circuit Blocks and Simulation Result: • Ring Oscillator • Phase Comparator • Majority Voting Circuit • Beat Frequency Detector • 8 Bit Counter Circuit • Total Circuit • Conclusion

  3. Abstract • Precise measurement of digital circuit degradation caused by aging • Reliability monitor using beat frequency of two ring oscillators to get a high sensing resolution • 1V, 32nm CMOS technology, up to 0.02% sensing resolution

  4. Overview • Introduction • Principle and background • Proposed reliability monitor circuit • Circuit Blocks and Simulation Result: • Ring Oscillator • Phase Comparator • Majority Voting Circuit • Beat Frequency Detector • 8 Bit Counter Circuit • Total Circuit • Conclusion

  5. Types of reliability issues • BTI (bias temperature instability) • HCI (hot carrier injection) • TDDB (time-dependent dielectric breakdown) • NBTI (negative bias temperature instability) • NBTI effect is among the most pressing issues among all of them

  6. Cause of NBTI effect • Structural mismatch at the Si-SiO2 interface cause dangling bonds • Si-H bonds is transformed by hydrogen passivation process of dangling Si bonds which is made by oxidation of Si-SiO2 • Broken bonds from Si-H degrade the driving current of pMOS threshold voltage • Positive shift in absolute value of pMOS threshold voltage |Vtp| in stress phase • Broken Si-H bonds is annealed in recovery phase, and Vtp is reduced

  7. Cross section of pMOS device and pMOS Vth degradation

  8. Constraints of typical measurement • Device probing, on-chip ring oscillator frequency monitoring • Limitations in sensing resolution, cannot get large number of data points

  9. Simulation platform • Microsoft Windows • HSPICE 2009 • CosmosScope

  10. Overview • Introduction • Principle and background • Proposed reliability monitor circuit • Circuit Blocks and Simulation Result: • Ring Oscillator • Phase Comparator • Majority Voting Circuit • Beat Frequency Detector • 8 Bit Counter Circuit • Total Circuit • Conclusion

  11. Beat frequency detection circuit

  12. Measuring difference in frequency between Stressed and Reference ROSC • When there is exactly one in the pulse difference between two ROSC, we can get the value of N before stress, and we use this method to get N’ which is detected after stress period.

  13. Beat frequency detection scheme • Using difference between stressed and reference ROSC • Before stress: N/fref=(N-1)/fstress • After stress: N’/fref=(N’-1)/f’stress • Percent of frequency degradation: • (f’stress-fstress)/fstress=(N’-N)/(N’(N-1))

  14. Change in counter output by frequency degradation • (f’stress-fstress)/fstress • =(N’-N)/(N’(N-1)) • When there is 1% degradation, N will decrease half compared with 1% for convention method

  15. Architecture of silicon odometer • Two ring oscillators, identical structure, different Vdd • Phase comparator will show frequency difference between two ROSC. • 5-bit majority voting circuit can erase the bubbles caused by jitter effect from phase comparator • Beat frequency detector can produce a DETECT signal to reset the counter, and get the output from the register

  16. Block diagram

  17. Overview • Introduction • Principle and background • Proposed reliability monitor circuit • Circuit Blocks and Simulation Result: • Ring Oscillator • Phase Comparator • Majority Voting Circuit • Beat Frequency Detector • 8 Bit Counter Circuit • Total Circuit • Conclusion

  18. Ring Oscillator

  19. Simulation Result of Ring Oscillator Circuit • The ring oscillator has a period of 4 ns

  20. Switch close Switch open Switch close X: Pre charge • CLK=0 Pre charge Phase Comparator • CLK=1 Evaluate • (Compare the phase of A and B) CLK=1 A’&&B=1 PC_OUT=1 CLK=1 A’&&B=0 PC_OUT=0 CLK=0 PC_OUT keep the same value

  21. CLK=0 PC_OUT keep the same value CLK=1 A’&&B=0 PC_OUT=0 CLK=1 A’&&B=1 PC_OUT=1 Simulation Result of Phase Comparator Circuit

  22. Majority Voting Circuit

  23. Majority Voting circuit (Continue)

  24. PC_OUT 10111010 Simulation Result of Majority Voting Circuit 10111011 VOTE_OUT 11111100 111111 00

  25. Beat Frequency Detector

  26. Simulation Result of Beat Frequency Detector Circuit Beat Frequency Latency 111111 00 10111 011

  27. 8 Bit Counter Circuit

  28. Simulation Result of 8 Bit Counter

  29. Simulation Result of Total Circuit

  30. CONCLUSION

  31. THANK YOU!

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