School of Computing Science Simon Fraser University CMPT 300: Operating Systems I

1. School of Computing Science Simon Fraser University CMPT 300: Operating Systems I Ch 8: Memory Management Dr. Mohamed Hefeeda

2. Objectives • To provide a detailed description of various ways of organizing memory hardware • To discuss various memory-management techniques, including paging and segmentation • To provide a detailed description of the Intel Pentium, which supports both pure segmentation and segmentation with paging

3. Background • Program must be brought (from disk) into memory and placed within a process to be run • Main memory and registers are the only storage CPU can access directly • CPU generates a stream of addresses • Memory does not distinguish between instructions and data • Register access in one CPU clock • Main memory can take many cycles • Cache sits between main memory and CPU registers to accelerate memory access

4. Binding of Instructions and Data to Memory • Address binding can happen at: • Compile time: • If memory location is known a priori, absolute code can be generated • must recompile code if starting location changes • Load time: • Must generate relocatable code if memory location is not known at compile time • Execution time: • Binding delayed until run time • process can be moved during its execution from one memory segment to another • Need hardware support for address maps • Most common (more on this later)

5. Multi-step Processing of a User Program

6. Logical vs. Physical Address Space • Logical address • generated by the CPU • also referred to as virtual address • User programs deal with logical addresses; never see the real physical addresses • Physical address • address seen by the memory unit • Both are the same if address-binding is done in • Compile time or • Load time • But they differ if address-binding is done in • Execution time •  we need to map logical to physical addresses

7. Memory Management Unit (MMU) • MMU: Hardware device that maps virtual to physical address • MMU also ensures memory protection • Protect OS from user processes, and protect user processes from one another • Example: Relocation register

8. Memory Protection: Base and Limit Registers • A pair of base and limit registers define the logical address space • Later, we will see other mechanisms (paging hardware)

9. Memory Allocation • Main memory is usually divided into two partitions: • Part for the resident OS • usually held in low memory with interrupt vector • Another for user processes • OS allocates memory to processes • Contiguous memory allocation • Process occupies a contiguous space in memory • Non-contiguous memory allocation (paging) • Different parts (pages) of the process can be scattered in the memory

10. Contiguous Allocation (cont’d) • When a process arrives, OS needs to find a hole large enough in the memory to accommodate it • OS maintains information about: • allocated partitions • free partitions (holes) • Holes have different sizes and scattered in the memory • Which hole to choose for a process? OS OS OS OS process 5 process 5 process 5 process 5 process 9 process 9 process 8 process 10 process 2 process 2 process 2 process 2

11. Contiguous Allocation (cont’d) • Which hole to choose for a process? • First-fit: Allocate first hole that is big enough • Best-fit: Allocate smallest hole that is big enough • must search entire list, unless ordered by size • Produces the smallest leftover hole • Worst-fit: Allocate the largest hole; • must also search entire list • Produces the largest leftover hole • Performance: • First-fit and best-fit perform better than worst-fit in terms of speed and storage utilization • What are pros and cons of contiguous allocation? • Cons: Memory fragmentation

12. Contiguous Allocation: Fragmentation • External Fragmentation • Total memory space exists to satisfy a request, but it is not contiguous • Solutions to reduce external fragmentation? • Memory compaction • Shuffle memory contents to place all free memory together in one large block • Compaction is possible only if relocation is dynamic, and is done at execution time • Internal Fragmentation • Occurs when memory has fixed-size partitions (pages) • Allocated memory may be larger than requested • the difference is internal to the allocated partition, and cannot being used

13. Paging: Non-contiguous Memory Allocation • Process is allocated memory wherever it is available • Divide physical memory into fixed-sized blocks called frames • size is power of 2, between 512 bytes and 8,192 bytes • OS keeps track of all free frames • Divide logical memory into blocks of same size called pages • To run a program of size n pages, need to find n free frames and load program • Set up a page table to translate logical to physical addresses

14. page number page offset p d m - n n Address Translation Scheme • Address generated by CPU is divided into: • Page number (p) – used as an index into a pagetable which contains base address of each page in physical memory • Page offset (d) – combined with base address to define the physical memory address that is sent to the memory unit • For given logical address space 2m and page size2n

15. Paging Hardware

16. Paging Model of Logical and Physical Memory

17. Paging Example Page size = 4 bytes Memory size = 8 pages = 32 bytes Logical address 0: page = 0/4 = 0, offset = 0%4 = 0 maps to  frame 5 + offset 0  physical address 20 Logical address 13: page = 13/4 = 3, offset = 13%4 = 1 maps to  frame 2 + offset 1  physical address 9

18. Free Frames After allocation Before allocation

19. Implementation of Page Table • Page table is kept in main memory • Page-table base register (PTBR) points to page table • Page-table length register (PRLR) indicates size of page table •  Every data/instruction access requires two memory accesses • One for page table and one for data/instruction •  use a special fast-lookup associative memory • Called Translation Look-aside Buffer (TLB) • Accelerates memory access • Stores part of page table (of currently running process) • TLBs store process identifier (address space identifier) in each TLB entry • provide address-space protection for that process

20. Paging Hardware With TLB

21. Effective Access Time • Associative Lookup =  time unit • Assume memory cycle time is 1 microsecond • Hit ratio  • percentage of times that a page is found in associative memory • Effective Access Time (EAT) EAT = ( + 1)  + ( + 1 + 1) (1 – ) = 2 +  – 

22. Memory Protection • Memory protection implemented by associating protection bit with each frame • Can specify whether a page is: Read only, write, read-write • Another bit (Valid-invalid) may be used to • “valid” indicates that page is in the process’ logical address space, and is thus a legal page • “invalid” indicates that the page is not in the process’ logical address space

23. Valid (v) or Invalid (i) Bit In A Page Table

24. Shared Pages • Shared code • One copy of read-only (reentrant) code shared among processes (i.e., text editors, compilers, window systems). • Shared code must appear in same location in the logical address space of all processes • Private code and data • Each process keeps a separate copy of the code and data • The pages for the private code and data can appear anywhere in the logical address space

25. Shared Pages Example

26. Structure of the Page Table • Hierarchical Paging • Hashed Page Tables • Inverted Page Tables

27. Hierarchical Page Tables • Break up the logical address space into multiple page tables • A simple technique is a two-level page table

28. Two-Level Page-Table Scheme

29. Two-Level Paging Example • A logical address (on 32-bit machine with 1K page size) is divided into: • a page number consisting of 22 bits • a page offset consisting of 10 bits • Since the page table is paged, the page number is further divided into: • a 12-bit page number • a 10-bit page offset • Thus, a logical address is as follows: • where pi is an index into the outer page table, and p2 is the displacement within the page of the outer page table page number page offset p2 pi d 10 10 12

30. Address-Translation Scheme

31. Three-level Paging Scheme

32. Hashed Page Tables • Common in address spaces > 32 bits • The virtual page number is hashed into a page table. This page table contains a chain of elements hashing to the same location. • Virtual page numbers are compared in this chain searching for a match. If a match is found, the corresponding physical frame is extracted.

33. Hashed Page Table

34. Inverted Page Table • One entry for each real page of memory • Entry consists of the virtual address of the page stored in that real memory location, with information about the process that owns that page

35. Inverted Page Table (cont’d) • Pros • Decreases memory needed to store each page table, • Cons • Increases time needed to search the table when a page reference occurs • Can be alleviated by using a hash table to reduce the search time • Difficult to implement shared pages • Because only one entry for each frame in the page table, i.e., one virtual address for each frame • Examples • 64-bit UltraSPARC and PowerPC

36. Segmentation • Memory management scheme that supports user view of memory • A program is a collection of segments. A segment is a logical unit such as: main program, procedure, function, method, object, local variables, global variables, common block, stack, symbol table, arrays

37. 1 1 4 2 3 4 2 3 user space physical memory space Logical View of Segmentation

38. Segmentation Architecture • Logical address has the form: • <segment-number, offset> • Segment table • maps logical address to physical address • Each entry has • Base: starting physical address of segment • Limit: length of segment • Segment-table base register (STBR) points to location of segment table in memory

39. Segmentation Hardware

40. Segmentation Example

41. Segmentation Architecture (cont’d) • Protection • With each entry in segment table associate: • validation bit = 0  illegal segment • read/write/execute privileges • Protection bits associated with segments  • code sharing occurs at segment level • Segments vary in length  • Memory allocation is a dynamic storage-allocation problem  • External fragmentation

42. Example: Intel Pentium • Supports segmentation and segmentation with paging • CPU generates logical address • Given to segmentation unit  produces linear address • Linear address given to paging unit  generates physical address in main memory

43. Pentium Segmentation Unit • Seg size up to 4GB • Max #segs per process 16 K • 8 K private segs  use local descriptor table • 8 K shared segs  use global descriptor table

44. Pentium Paging Unit • Page size either: • 4 KB  two-level paging • 4 MB  one-level paging

45. Linux on Pentium • Linux is designed to run on various processors • three-level paging (to support 64-bit architectures) • On Pentium, the middle directory size is set to 0 • Limited use of segmentation • On Pentium, Linux uses only six segments

46. Summary • CPU generates logical (virtual) addresses • Binding to physical addresses can be static (compile time) or dynamic (load or run time) • Contiguous memory allocation • First-, Best-, and worst-fit • Fragmentation (external) • Paging: noncontiguous memory allocation • Logical address space is divided into pages, which are mapped using page table to memory frames • Page table (one table for each process) • Access time: use cache (TLB) • Size: use two- and three-levels for 32 bits address spaces; use hashed and inverted page tables for > 32 bits • Segmentation: variable size, user’s view of memory • Segmentation + paging: example Intel Pentium