1 / 6

DPPM for Analog and RF Circuits

DPPM for Analog and RF Circuits. Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA vagrawal@eng.auburn.edu Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA szs0063@auburn.edu 32nd IEEE VLSI Test Symposium Napa, California April 14, 2014. Problem Statement.

skah
Télécharger la présentation

DPPM for Analog and RF Circuits

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. DPPM for Analog and RF Circuits Vishwani D. Agrawal Auburn University, Auburn, AL 36849, USA vagrawal@eng.auburn.edu Suraj Sindia Intel Corporation, Hillsboro, OR 97124, USA szs0063@auburn.edu 32ndIEEE VLSI Test Symposium Napa, California April 14, 2014

  2. Problem Statement • Given: • Aset of complete specification-based tests for an analog or RF circuit, and • An acceptable defect level (DL), • Find the smallest set of tests that should be used. LATW 2014: Spec. Test Minimization

  3. A Bipartite Graph Tests T1 T2 T3 T4 p12 p33 p13 p11 p44 p22 p42 p21 p34 S2 S1 S3 S4 Specifications LATW 2014: Spec. Test Minimization

  4. Operational Amplifier: TI LM741 LATW 2014: Spec. Test Minimization

  5. Test Minimization LATW 2014: Spec. Test Minimization

  6. Conclusion • Specification tests are given. • Monte Carlo spice simulation determines probability, pij, of ith test checking for jth specification. • An integer linear program (ILP) determines the defect level for any number of tests. • References: • S. Sindia and V. D. Agrawal, “Specification Test Minimization for Given Defect Level,” Proc. 15th IEEE Latin-American Test Workshop, Fortaleza, Brazil, March 13, 2014. • A detailed paper submitted to ITC 2014. LATW 2014: Spec. Test Minimization

More Related