PXL System Hardware Architecture

1. PXL System Hardware Architecture

2. Talk Outline • Revisit Requirements. • Overall Architecture. • Design Choices. • Summary.

3. PXL System Requirements • Interface to the sensors for readout and control. • Triggered detector system fitting into existing STAR infrastructure (Trigger, DAQ, etc.) • Deliver full frame events to STAR DAQ for event building at approximately the same rate as the TPC (1 kHz for DAQ1000). • Have live time characteristics such that the Pixel detector is live whenever the TPC is live. (PXL adds ≤ 5% additional dead time) • Reduce the total data rate of the detector to a manageable level (< TPC rate of ~1MB / event). • Reliable, cost effective, etc. • Provide additional functionality for sensor testing including production probe testing.

4. Pixel Detector Characteristics • Two concentric layers at 2.5 & 8 cm radii • 10 sensors/ladder, 4 ladders/module (arm), 10 modules/detector. • MAPS Pixel technology • Sensor spatial resolution < 10 μm • Coverage 2πin φand |η|<1 • Over 400 M pixels on ~0.16 m2 of Silicon • 0.37 % radiation length/layer • MCS limited resolution • Thinned silicon sensors (50 μm thickness)‏ • Air cooled • Sensor power dissipation ~170 mW/cm2 • Quick extraction and detector replacement • Mechanical stability and insertion reproducibility within a 20 μm window • Integration time <200 μs (L=8×1027) • Radiation environment at the level of up to 20k – 90k rad/year and 1011 -1012/cm2Neq /year

5. System Constraints • We need FPGA processing to do zero suppression (Phase-2) and event building. This necessitates moving the processing out of the high radiation area. (SEU) • The constraint of locating the event fast pre-processing hardware ~7m from the sensors (in a lower radiation area) requires a driver/mass termination board located between the sensors and the processing hardware. This is required for mechanical and signal integrity reasons. • This provides additional benefit that the main part of the electronics is in an area that is serviceable during a cave access. • This leads to a 3 main component architecture.

6. PXL Hardware Architecture Ladder RDO motherboard Mass Termination Board

7. PXL Hardware Architecture

8. PXL Hardware Architecture

9. PXL Hardware Architecture

10. Functional Data Path – One Ladder buffer buffer Develop readout electronics (WBS 1.2.2.5) 10 sensors 1 Ladder JTAG, CLK, CTL, markers LU protected power Digital hit data • After power-on and configuration, the sensors are run continuously. • Triggering is handled in the next stage of the RDO.

11. Functional Data Path – Phase-1 Highly Parallel FPGA based RDO system • 40 sensor outputs/ladder • 1 sector / RDO board • Each received trigger enables an event buffer for one frame. • The system is dead-time free up to the hardware buffering limit. 160 independent sensor data chains

12. Functional Data Path – PXL Sensor Highly Parallel FPGA based RDO system • 20 sensor outputs/ladder • 1 sector / RDO board • Same hardware with reconfigured firmware

13. RDO System Design – Physical Layout Sensors / Ladders / Sectors (interaction point) RDO Boards 1-2 m Low mass twisted pair LU Protected Regulators, Mass cable termination Platform 30 m Power Supplies 6 m - twisted pair 30 m 100 m - Fiber optic Control PCs 30 m DAQ Room DAQ PCs (Low Rad Area)

14. PXL RDO Basic Unit Develop readout electronics (WBS 1.2.2.5) 2m 6m RDO PC 100m • 4 ladders per sector • 1 Mass Termination Board (MTB) per sector • 1 sector per RDO board • 10 RDO boards in the PXL system

15. Ladder Constraints • 10 sensors to give required eta coverage • Radiation length budget dedicated to cable/sensor assembly (0.17%) in low mass region. • Sensors thinned to 50 µm (X/X0 ~0.053%) • Al conductor 2 sided cable (X/X0 ~0.08%) • Mechanical stiffener between cable and sector tube. • Buffering for all signals to/from ladder. • Fine twisted pair wire interface to ladders.

16. Ladder Design The ladder consists of three main elements 10 x sensors adhesive Kapton flex cable adhesive Carbon fiber stiffener plate • Thinning sensors to 50 µm is a standard commercial process. • The adhesive is a 50 µm acrylic film adhesive. • The carbon fiber stiffener plate is a basket weave 90º prepreg. • The flex cable is the component that requires a significant development effort.

17. Flex Cable Development http://rnc.lbl.gov/hft/hardware/docs/cd1/PXL_flex_cable_and_sys_test_v2.doc There are 4 stages to the development process • Stage1 – Infrastructure Testing Board - evaluate the general design of running 10 sensors on a ladder and find and test the working envelope of bypass capacitance and power supply and ground connection • Stage 2 – FR-4 ladder cable prototype with Cu - Taking the knowledge gained in the Infrastructure Test Phase, we now attempt to fit the readout cable traces into the required size of the ladder readout cable. • Stage 3 – Kapton ladder cable prototype with Cu – Translate above design to kapton flex. • Stage 4 – Kapton ladder cable with Al – production prototype for the final ladder cable.

18. Flex Cable Development Preliminary Design: Hybrid Copper / Aluminum conductor flex cable Side view (exaggerated vertical scale) Top View • 2 layer Al conductor cable in low mass region • 0.004” (100 µm) traces and 0.004” (100 µm) spaces • 70% fill factor • Conductor thickness in low mass region is 21 µm (Cu) or 32 µm (Al) • Minimum required conductor trace width 1.325” (33.65 mm) of 46.16 mm available. • Bond wire connection between Al and Cu cable sections. Low mass region calculated X0 for Al conductor = 0.073 % Low mass region calculated X0 for Cu conductor = 0.232 %

19. MTB Design • Services 1 sector (4 ladders) • Buffers for all signals to and from ladders • ADC for temperature measurement of sensors • LU protected power daughter-card for each ladder • PLL to regenerate 50% duty cycle clock

20. RDO motherboard design constraints • 320 input data pins for Phase-1/2 sensor data / sector. • 160 input data pins for Final sensor data / sector. • JTAG, sensor CLK, etc. generation. • IODELAY function (Xilinx Virtex). • ALICE DDL interface to STAR DAQ. • STAR trigger interface. • USB interface • Sensor testing capabilities (one development platform) • 8 ch ADC (50 MHz) • Fast SRAM for full frame event capture • Misc logic inputs for control / triggering (beam tests)

21. RDO motherboard design The RDO board is a 2 board design RDO Motherboard Sensor data interface Sensor control interface Virtex-5 interface STAR Trigger interface QuickUSB interface PMC interface (DDL) 8 ch 50 MHz 12b ADC 144Mb SRAM Auxiliary logic interface Virtex-5 Daughtercard JTAG interface RDO MB int.

22. RDO motherboard design The RDO board is a 2 board design Xilinx AFX-FF1760-500 Custom Motherboard Xilinx XC5VLX330 10,638 Kb block RAM 1200 i/o 6 layer Standard PCB “5 on 5” No BGA

23. RDO motherboard design comments • The complete RDO system for PXL consists of 10 RDO motherboard assemblies. • Investment in a ≥ 16 layer custom RDO motherboard with BGA Xilinx V-5 is not warranted for this quantity. • Additional testing functionality need not be loaded for production RDO boards. • This design allows for a single development platform through the full project life cycle.

24. Parts Specifications Ladder components MAPS sensor FIN1108 Fairchild LVDS 8 Port Repeater SN74LVC126A TI Quad Bus buffer gate SN65LVDS2 TI Single LVDS receiver High radiation area MTB components FIN1108 Fairchild LVDS 8 Port Repeater SN65LVDT14 TI Interconnect Extender Chipset w/ LVDS SN65LVDT41 TI Interconnect Extender Chipset w/ LVDS AD7997 Analog Devices 8-ch, 10-bit I2C ADC CY7B9950 Cypress 200MHz PLL Clock Buffer MIC37152 MICREL 1.5A LDO Voltage Regulator AD626 Analog Devices single supply diff. amplifier AD8611 Analog Devices single supply comparator polyfuses Moderate radiation area

25. Simple Data Rates Phase-1/2 Final (Ultimate) Raw data rate from sensors = 32 GB/sec Data rate to storage = 237 MB/sec Data rate to storage = 199 MB/sec (Scaled to full size detector) (199 kB/event) Note: Data rates for hit data only for Au-Au central collisions including peripheral collision electrons. Sensor noise is not included.

26. Summary • We have a well developed system architecture that is driven by the tracking, mechanical and testing constraints. • Highly parallel system based on ladder and sector units. • FPGA based data receiver and processing. • Leverages commercial Xilinx development boards mated to a custom motherboard. • Single architectural unit to provide for all required development and testing.

27. Backup

28. PXL Detector Design Cabling and cooling infrastructure New beryllium beam pipe (800 µm thick, r = 2.5 cm)‏ Mechanical support with kinematic mounts 2 layers 10 modules 4 ladders/module Detector extraction at one end of the cone Ladder with 10 MAPS sensors (~ 2×2 cm each)

29. Sensor Generation and RDO Attributes Gen Sensor Sensor RDO Mimostar–2 30 µm pixel, 128 x 128 array 1.7 ms integration time 1 analog output Mimostar–3 30 µm pixel, 320 x 640 array 2.0 ms integration time 2 analog outputs Phase–1 30 µm pixel, 640 x 640 array 640 µs integration time, CDS 4 binary digital outputs PXL Sensor (Ultimate) 18.4 µm pixel, 1024 x 1088 array ≤ 200 µs integration time, CDS, zero suppression 2 digital outputs (addresses) 50 MHz readout clock JTAG interface, control infrastructure ADCs, FPGA CDS & cluster finding zero suppression ≤ 4 sensor simultaneous readout 160 MHz readout clock JTAG interface, control infrastructure zero suppression 40 sensor simultaneous readout 160 MHz readout clock JTAG interface, control infrastructure 400 sensor simultaneous readout (full system) 1 DONE 1 2 PROTOTYPED 3

30. Sensor / RDO Services (preliminary) 4800 × 42 AWG (TP) 160 × 24 AWG (TP) 1100W (AC) Platform (racks) 10 × USB 2 × TCD (10 TP) 28 × 12 AWG ~30m MTB PP Ladders 180W 300W 6m 240 W RDO Crate 2m 10 × fiber optic cable pair ~100m 1350W (AC) 40 × 0.42” dia. (50 TP cable) 20 × 16 AWG DAQ Room