1 / 67

Signal Integrity Challenges for 100 Gb Systems

Signal Integrity Challenges for 100 Gb Systems. IEEE Communications Society-Silicon Valley Chapter July 13 th , 2011 Lux Joshi Product Specialist lux.joshi@lecroy.com. Agenda. Motivation Overview of 100 Gb Links Standards Architecture of 100 Gb Systems Implementations Signal Integrity

wiegand
Télécharger la présentation

Signal Integrity Challenges for 100 Gb Systems

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Signal Integrity Challenges for 100 Gb Systems IEEE Communications Society-Silicon Valley Chapter July 13th, 2011 Lux Joshi Product Specialist lux.joshi@lecroy.com

  2. Agenda • Motivation • Overview of 100 Gb Links • Standards • Architecture of 100 Gb Systems • Implementations • Signal Integrity • Channel Modeling • Equalization • Jitter • Crosstalk

  3. Motivation The need for increased bandwidth continues Bandwidth Growth Forecasts according to IEEE802 2007 HSSG Source: IEEE 802.3ba HSSG, 2007

  4. Consumer Internet Video drives IP Traffic Demand Source: Cisco Whitepaper Approaching the Zetabyte Era, 2008

  5. Headlines

  6. Bottlenecks in Telecom Infrastructure • IP backbone and Optical Transport (OTN) • Metro Area Carrier Networks • Wireless Backhaul • Content provider networks (OLTs/PONs?) Source: IEEE 802.3ba HSSG, 2007

  7. Solutions • Solutions • Wider Data Paths • Requires Additional Installations/Infrastructure • Economy of Scale for components • Higher Data Rates • Requires New Technology Developments • Re-use Existing Infrastructure (possibly)

  8. Optimization Considerations • Aggregate Network Bandwidth • Latency • Power • Complexity • Density • Cost

  9. Optimization Considerations • Aggregate Network Bandwidth (+) • Latency (constant) • Power (+/-) • Complexity (-) • Narrower Buses, less I/O • Faceplate Density (+) • More I/O per rack • Cost (Capex vs. Opex tradeoffs) • Up Front System Costs - Capex • Power and Size - Opex

  10. Standards

  11. Standards Bodies for the 100G Ecosystem Relevant standards bodies • Fosters development and deployment of interoperable products […] using optical networking technologies. • Implementation agreements (IA) -> Multisource Agreements (MSAs) United Nations agency for information and communications technology issues and the global focal point […] in developing networks and services. 802.3ba: Standard for Ethernet applications at 40 Gbps and 100 Gbps transfer rate  Standards 11

  12. Standards Bodies for the 100G Ecosystem Relevant standards bodies • Fosters development and deployment of interoperable products […] using optical networking technologies. • Implementation agreements (IA) -> Multisource Agreements (MSAs) United Nations agency for information and communications technology issues and the global focal point […] in developing networks and services. 802.3ba: Standard for Ethernet applications at 40 Gbps and 100 Gbps transfer rate  Standards 12

  13. Standards Bodies for the 100G Ecosystem Relevant standards OIF-CEI25/28G and related ITU-T G.709 (OTU4) IEEE802.3ba - 2010 13

  14. 100 Gb Ethernet Standards • IEEE 802.3-ba standards based on 100GBASE-R PCS • 64/66B Encoding • Full Duplex

  15. 100 Gb Ethernet Standards • IEEE 802.3-ba standards based on 100GBASE-R PCS • 64/66B Encoding • Full Duplex

  16. 100 Gb/s Standards (con’t) • OIF-CEI-25/28G standards (in Progress)

  17. 100 Gb/s Standards (con’t) • ITU-OTU4

  18. 193.10 THz 1552.52 nm 198.5 THz (Supervisor) 192.10 THz 192.20 THz 193.0 THz 193.20 THz 196.10 THz N x 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm N x 0.4 nm N x 50 GHz N x 50 GHz 50GHz 50GHz 50GHz 50GHz 50GHz 50GHz l (nm) 100 GHz 100 GHz 100 GHz 100 GHz 100 GHz N x 0.8 nm 0.8 nm N x 0.8 nm 0.8 nm 0.8 nm Limited Bandwidth of Installed Optical Spectrum • Dense Wavelength Division Multiplexing • 50 GHz carrier spacing for installed DWDM equipment • 100 Gb/s pushes spectrum of information to this limit

  19. 100 Gb System Architecture

  20. Basic Architecture of 100 Gb Ethernet Physical Layer • PCS • 64/66B Encoding • Lane Distribution and Alignment • FEC • Optional Encoding Layer • PMA • I/O to PMD • Clock Generation/Recovery • Lane Assignment • PMD • Interface and drive transmission med • AN • Optional layer to interpret link operation primitives (link speed, capability, status, etc.) Source: IEEE 802.3ba-2010 Standard

  21. 1st Generation PMD Modules • Current Available Physical Medium Dependent (PMD) module • Uses CAUI Bus (10x10 Gb/s) I/O from PCS to PMA • Uses Wavelength Division Multiplexing (WDM) to interface to fiber medium Current CFP PMD Module Source: Ethernet Technology Summit, Ed Farlan, Gennum

  22. 2nd Generation PMD Modules • Uses CEI-28G-VSR Bus (4x28 Gb/s) I/O from to PMA to PMD. • PMA located on line card with PCS • Narrower faceplate profile -> Higher faceplate density • Possible 3rd Generation architecture under study • Uses unretimed optical module • Smaller profile • Risk of higher bit error rate Future CFP PMD Module architecture Source: Ethernet Technology Summit, Ed Farlan, Gennum

  23. 193.10 THz 1552.52 nm 198.5 THz (Supervisor) 192.10 THz 192.20 THz 193.0 THz 193.20 THz 196.10 THz N x 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm 0.4 nm N x 0.4 nm N x 50 GHz N x 50 GHz 50GHz 50GHz 50GHz 50GHz 50GHz 50GHz l (nm) 100 GHz 100 GHz 100 GHz 100 GHz 100 GHz N x 0.8 nm 0.8 nm N x 0.8 nm 0.8 nm 0.8 nm Limited Bandwidth of Installed Optical Spectrum • Limited bandwidth on ITU grid • 50 GHz carrier spacing for installed DWDM equipment • 100 Gb/s pushes spectrum of information to this limit • Dispersion (CD and PMD) limits transmission distance for high direct modulation rate

  24. t Ultra-high Speed Transmission Technologies DP-QPSK - OIF Ultra Long-Distance Transmission This project has adopted dual polarization quadrature phase shift keying (DP QPSK), [also called PM-QPSK when using the PM abbreviation for Polarization Multiplexing instead of Dual Polarizationmodulation] with a coherent receiver. Vertical Polarization Dual Polarization DGD (differential group delay) Horizontal Polarization

  25. High Speed Optical Transmission DP-QPSK - Block diagram of a DP-QPSK transmitter module IQ 25 Gsymbols/s (50GBit/s) I 25G Base band data stream #1 Q 25G Base band data stream #1 100GBit/s I 25G Base band data stream #1 Q 25G Base band data stream #1 IQ 25 GSymbols/s (50GBit/s) BS: Beam Splitter BC: Beam Combiner Pol Rot: Polarization Rotator

  26. Signal Integrity

  27. Signal Integrity Overview • Types of Signal Integrity Degradation and their typical causes • Assume Electrical PCB transmission. Optical issues will not be discussed **Jitter as classified here refers to random jitter (Rj) and possibly periodic jitter (Pj) from EMI. ISI can cause data dependent jitter which is a specific type of deterministic jitter (Dj)

  28. Channel Quality for Backplane Applications

  29. Optics Optics Optics Optics Chip Chip Chip Chip Chip Chip Chip Chip Chip Chip CEI Application Space Chip-to-Optics, No or Partial Retiming in Optics Module CEI-28G-VSR Chip-to-Optics, Full Retiming in Optics CEI-28G-SR Chip-to-Chip Passive Copper Cable CEI-25G-LR Backplane Source: Ethernet Alliance TEF; David Stauffer

  30. CEI-28 Very Short Reach Channel • Chip-to-optics standards must support 28.05 Gb/s to support 4-lane OTU-4 interfaces. • Chip-to-optics channel budget: • Host Signal Trace: 4“ of advanced material (6dB) • Connector: 2dB insertion loss • Module Signal Trace: 2“ of signal trace & decoupling cap (4 dB) Source: Ethernet Alliance TEF, David Stauffer

  31. CEI-28G Short Reach Channel • Chip-to-chip standards must support 28.05 Gb/s to support 4-lane OTU-4 interfaces. • Chip-to-chip applications must budget for 12 inches of reach with 1 connector. • Channel limits to achieve technical feasability: • Insertion loss limit of-15.5 dB at 14.0 GHz. • Specify limits for Insertion Loss Deviation & crosstalk. Source: Ethernet Alliance TEF, David Stauffer

  32. CEI-25 Long Reach Channel • Backplane standards must support 25.78125 Gb/s to4-lane 100G interfaces. • 30 inches of reach with 2 connectors. • Channel limits: • Insertion loss limit of-25.5 dB at 12.9 GHz. • Specify limits for Insertion Loss Deviation & crosstalk Source: Ethernet Alliance TEF, David Stauffer

  33. Requirements for backplane • NRZ Signaling format chosen • Number of studies indicate no benefit of PAM encoding at 25 Gb/s • In addition no widespread commercial development of PAM Xceivers • Advanced Equalizer Requirements • Multi-tap Tx FFE • 17 dB Rx CTLE + Multi-tap Rx DFE • Call for Evolution in PCB and connector technologies • Target 1.5x per lane power increase per lane vs. 10 Gb/s lanes • Overall 60% less power dissapation (goal but not reality today)

  34. PCB Materials Cost Comparison Source: Ethernet Alliance TEF, Joel Goergen

  35. Insertion Loss for LR channels Nyquist for 25 Gb/s Source: MeghaShanbhag, TE Connectivity. Full Data Set available at http://www.ieee802.org/3/100GCU/public/channel.html

  36. Intersymbol Interference (ISI) Insertion Loss and Impulse Response of 29 inch Megtron-6 Channel

  37. Intersymbol Interference (ISI) Input to Channel Channel Output Low frequency transitions propagate relatively untouched

  38. Intersymbol Interference Input to Channel Channel Output High frequency transitions become attenuated causing Inter symbol Interference (ISI)

  39. What is Equalization? Transmit equalization pre-distorts signal in anticipation of the channel (e.g. boosts high frequency content) to reduce ISI Linear receive equalization undoes channel effects Decision feedback equalization (DFE) feeds back level changes based on previous data Receiver DFE CTLE FFE Transmitter

  40. Equalization

  41. Backplane Signal Integrity Case Study

  42. Backplane Case Study Setup • Daughter card-Backplane-Daughter Card Setup • 5”-17”-5” trace length + connectors Data and Schematic Courtesy TE Connectivity

  43. Signal Integrity Overview **Jitter as classified here refers to random jitter (Rj) and possibly periodic jitter (Pj) from EMI. ISI can cause data dependent jitter which is a specific type of deterministic jitter (Dj)

  44. Channel Data Insertion Loss and Impulse Response of 30 inch Megtron-6 Channel

  45. Received Eye Receiver Transmitter ＣＨＡＮＮＥＬ

  46. Equalizer Response Backplane Insertion Loss 1st Order Linear Equalizer Response 14 dB Boost

  47. Received Eye CTLE Only Receiver Transmitter CTLE ＣＨＡＮＮＥＬ + Digital Analog

  48. Received Eye CTLE and 3-tap DFE Receiver Transmitter CTLE DFE ＣＨＡＮＮＥＬ + Digital Analog

  49. Equalization can recover closed eyes 25 Gb/s Eye Diagram at transmitter output 25 Gb/s Eye Diagram after equalization

  50. Signal Integrity Overview **Jitter as classified here refers to random jitter (Rj) and possibly periodic jitter (Pj) from EMI. ISI can cause data dependent jitter which is a specific type of deterministic jitter (Dj)

More Related