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Status of the electronics systems of the MEG experiment

Status of the electronics systems of the MEG experiment

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Status of the electronics systems of the MEG experiment

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  1. Status of the electronics systems of the MEG experiment

  2. HV 1:1 1:1 Active Splitter Active Splitter 1:1 1:1 Trigger 216 4:1 4:1 Trigger front PMT atten Trigger LXe 612 lateral PMT 3 crates HV DRS DRS 1:1 Active Splitter 60 120 DRS bars PMT Ramp 1:1 DRS 4:1 TC DRS HV DRS 8:1 APD Pre-Amp fibers 640 6 crates HV Hit registers 32 Wires Pre-Amp 576 DC 1156 4 boards Strips Pre-Amp Aux. devices Electronic chain

  3. pE5 area ‘counting room’ Trigger Trigger Trigger Trigger clock start stop sync Front-End PCs Main DAQ PC PC (Linux) PC (Linux) PC (Linux) PC (Linux) Run start Run stop Trigger config PC (Linux) DRS PC (Linux) DRS Busy Error PC (Linux) DRS DRS PC (Linux) DRS PC (Linux) DRS 20 MHz clock PC (Linux) Hit registers Event builder PC (Linux) PC (Linux) Gigabit Ethernet Trigger signal Event number Trigger type PC (Linux) PC (Linux) On-line farm storage DAQ and control Ancillary system 3 crates 6 crates

  4. HV

  5. HV System 4 different requirements: • Lxe: 1000V , 100 uA • TC bars: 2400V, 1 mA • TC curved: 500V, <1 uA • DC: 2400V, ~1 uA • System works from 10V – 2400V, 1.5mA, 1uAresolution, special version for 1nA resolution • Current-trip feature implemented and tested, the HV-off time determined by de-charging capacitance • HV will “end” at backplane • ‘Users’ have to decide about connectors • 4-channel system in 3HE crate (40 channels are currently in use at PSI) • 10-channel system in 6HE crate 400 channels in preparation, ready by September http://www.fischerconnectors.com/ 1-15 kV

  6. HV crate • 10 chn per board • 180 chn per 3 HE crate • Back side connector HV passes through backplane

  7. Splitters

  8. input DRS output test Trigger or Spare output DRS or trigger summed output Splitter – project requirements • Inputs: • 828 Lxe + 120 TC channels • Single ended (Rin=50Ω) • Dual row headers connectors • Test: • High-precision and constant amplitude levels • Outputs: • DRS: • Full bandwidth • Gain ~ 1 • Trigger: • 100 MHz bandwidth • Gain ~ 1 • Analog Adder: • 4-channels sum • 100 MHz bandwidth • Gain ~ 1 • Differential (Rout=120Ω) • Standard profile boxed header connectors (3M • Dynamic range: • Limited into 0V - 2.5V • Card size and density: • Standard double Eurocard (6U) • 16 channels per card

  9. Components selected • THS4509 – 1.9GHz, 6600 V/μs Low Distortion fully Differential Amplifier • DRS outputs driver; • AD8137 – Low Distortion Differential ADC Driver • Trigger and sum output driver.

  10. Prototype • In the first half of 2005 the technical requirements for splitter were defined • The final prototype design started immediately • The 2-channels prototype was completed in March 2005 and tested

  11. Crosstalk test • Input pulse: • 1.6V amplitude (Vout+=+0.8V, Vout-=-0.8V) • <1 ns risetime • Input crosstalk (Metallic enclosure) • Crosstalk Ch1→Ch4: <0.1%; • Crosstalk Ch2→Ch4: ~0.5%; • Crosstalk Ch3→Ch4: ~1.5%; • Inside the board + output connector crosstalks (input connector contribution excluded) • Crosstalk Ch3→Ch4: ~1.5% • Inside the board crosstalk • Crosstalk Ch3→Ch4: ~0.5%;

  12. Final splitter board Full BW Output (34-pins) Input (64-pins) Sum output (16-pins) Reduced BW Output (34-pins) Power and test

  13. Test circuit • The calibration of the DRS channels needs constant levels voltage on all inputs • A step voltage generator, with 4 voltage levels, was developed • Levels are defined with high precision low noise reference IC (LM4140) with 0.1% accuracy and low temperature coefficient (3ppm/°C) • This circuit will be implemented on the backplane and it will feed all the splitter cards contained in the crate.

  14. Production • October 05 – test of the final prototype • December 05 – end of full production • October 05 – order of the cables • March 05 – installation

  15. TC

  16. PMT ramp generator B to Splitter Analog signals to DRS and trigger PMT B S TC Analog Sign. Monitor Passive Splitter RAMP GEN. D/D 6U Eurocards boards 8 boards to Splitters Signals to DRS Dual Threshold Discriminator NIM Signal for any possible use

  17. Kapton Flex. APD Black Coating Electronics boards -10 channels Scint. Fibers Transition board Copper Cold Finger(~20°) Peltier Cell Heat Exchanger • Input: 10 APD • Ouput: • 10 shaped and discriminated channels for the hit register • 1 analog sum for the trigger • ENC: 1500 e rms • Risetime:5 ns • Pulse-length: 50 ns APD pre-amplifier

  18. Hit encoder/register 6U VME boards 5 boards 152 Curved TC right side Curved TC left side 152 A*B Mask Right Mask Left 152 Clock control signal Encoder Control Logic Trigger and monitor VME bus Register FPGA

  19. Production PMT ramp generator • October 05 – design of the final board • January 06 – system delivery (8 boards - 6U Eurocards) APD pre amplifiers • September 05 – design of the final APD pre-amplifiers • October 05 – test of the final prototype • December 05 – system delivery (80 cards) APD hit registers • December 05 – board design • April 06 – system delivery (6 boards – 6U VME)

  20. DC

  21. right left up + up - down + down - At interface He bag – outside Cobra DC electronics inverting anode OR small R Preamplifier 16 x (2 x 9) x 6 = 1728 channels 16 ch. cable to DRS cathode OR Large R Non inverting

  22. Production DC electronics • September 05 – design of the final pre-amplifiers • November 05 – test of the final prototype • January 06 – system delivery

  23. Trigger

  24. 14 boards . . . Type2 Type2 Type2 Type2 Type2 14x 48 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 Type1 4 4 4 4 16 16 16 16 16 9 boards . . . 9x 48 Trigger system structure 2 boards 2 VME 6U 1 VME 9U Located on the platform LXe inner face (216 PMTs) 2 x 48 9+2 boards . . . 1 board LXe lateral faces back (216 PMTs) 4 in 1 lat. (144x2 PMTs) 4 in 1 up/down (54x2 PMTs) 4 in 1 9 x 48 2 x 48 1 board 2 x 48 Timing counters curved (640 APDs) 8 in 1 u/d stream (30x2 PMTs) 1 board 2 boards Drift chambers 16+16 channels 2x 48

  25. Type1 Present Status CPLD : Coolrunner II (XC2C284-10-FG324)  • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP20-7-FF1152) • Type1-1: LXe front face (Frequency 116 MHz) • Type1-2 LXe lateral faces in progress~ • Type1-3 TCx • Type1-4 DC x PCB : • import FPGA • Board Schematics • Footprints and routing  • Gerber files  • PCB production in progress • Board mountingx

  26. Type1

  27. Type2 Present Status CPLD : Coolrunner II (XC2C284-10-FG324)  • Type1 : CPLD design completed and simulated FPGA : VIRTEX II- PRO (XC2VP40-7-FF1152) • Type2-0 Final Level completed   • Type2-1 LXe inner faces x • Type2-2 LXe lateral faces x • Type2-3 TCx PCB : • import FPGA • Board Schematics  • Footprints and routing  • Gerber files  • PCB production in progress • Board mountingx

  28. Type2

  29. Ancillaryboards Type2 Type2 Type2 Type1 Type1 Type1 Type1 Type1 Type1 5 5 5 5 2 5 2 5 Event counter Trigger pattern to DRS Busy from DAQ START STOP START STOP SYNC RES CLK ANCILLARY Mother . . . CLK 20 MHz SYNC RES VME ANCILLARY Daughters 60 x CLK to DRS

  30. Ancillary Present Status CPLD : Coolrunner II (XC2C284-10-FG324)  • Type1 : CPLD design completed and simulated Components : MAX9153 – 3D3418 PCB : • import FPGA • Board Schematics  • Footprints and routing in progress • Gerber files x • PCB production x • Board mountingx

  31. Trigger components All components already delivered, including LVDS interconnect cables

  32. Trigger test • The test of the final boards can be done in September, as foreseen in the schedule • The test will be done by using Struck interfaces. The present read-out speed of all trigger WFS for the full system is around 15 Hz. • This rate is more than adequate for the trigger system needs: calibration, efficiency measurements and stability • We are investigating the possibility of increasing the readout speed.

  33. Trigger schedule 2002 2003 2004 2005 Prototype Board Final Prototype Full System partial installation Prototype Board Final Prototype Full system 1st lot of components ordered full install. 2nd lot of components Design Manufactoring Assembly Test Milestone

  34. Domino chip status

  35. 674 additional chips produced 150 chips for MAGIC 4200 channels for DC/TC/LXe DRS2 plastic PLCC

  36. Improved Sampling Range Domino wave can be operated below 500 MHz if started with a longer starting pulse. Minimum is ~5 MHz. Modified start pulse makes operation at 500 MHz stable.

  37. Spikes in last beam time

  38. Cause of spikes At 33 MHz, spike is always sampled, independent of FADC phase At 16.5 MHz, FADC phase can be adjusted to skip spike

  39. Fixing spikes before Spikes were fixed by reducing readout speed from 33 MHz to 16.5 MHz. Longer dead time will be compensated by having two FADCs in new mezzanine board after

  40. Double Peaks Double peaks in signals were caused by crosstalk from domino tap signal used for domino frequency measurement Domino Tap signal crosstalk Fix: different routing, multilayer, ground shield Clock signal

  41. CMC connection

  42. Timing Stability Frequency Stabilization Trigger Signal Sampling domino wave FADC 8 inputs Freq. Cntr FPGA 16-bit DAC shift register Implemented in FPGA (VHDL) → 400 ps stability Low-jitter clock MUX

  43. Recovery of Timing 4) Timing of all PMT pulses is expressed relative to t=0 point 1) Trigger publishes phase f of trigger signal f relative to clock in multiples of 10 ns f 50 ns 2) Each DAQ card determines and fits “Time-Zero-Edge” in clock signal and uses this as t=0 3) Measure pulse width of clock to derive domino speed Domino speed stability of 10-3 : 400ps uncertainty for full window 25ps uncertainty for timing relative to edge

  44. Domino wave jitter 30 ns • 33 MHz calibration clock • Peak fit with reference pulse • Average over all pulses for many events • Jitter is 115 ps • Maximum distance of any signal to next clock peak is 15 ns → accuracy should be ~60 ps

  45. Calibration • Measure Vin – Vout characteristics with precise DC power supply at the DRS2 input for all bins • Fit characteristics and use it for calibration • One curve needed per bin, under improvement • Is now done offline, will later be done online (front-end or FPGA) mV ADC counts / 10

  46. Effect of calibration • Calibration in mV • “Fixed pattern noise” is gone • Crosstalk from clock remains

  47. Noise Measurement Trigger mV 0.55 mV / 1V > 11 bits mV

  48. Crosstalk inside DRS • Measured with signal generator • Current crosstalk is not good but acceptable for the moment • Since integral of crosstalk is zero, it should mainly affect the timing and pile-up recognition • Expect crosstalk in DRS3 (differential inputs) smaller by ~5x + =

  49. Current readout mode • First implemented in DRS2 • Sampled charge does not leave chip • Current readout less sensitive to cross-talk etc. R I Vin Vout read write . . . C I = c1 * Vin + c2 * Vin * kT

  50. Temperature Dependence Tc ~ 1.4 % / ºC Vout [V] T [º C] DRS2 has a marked dependence on the temperature