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Fundamentals of Programming Languages-II

Fundamentals of Programming Languages-II

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Fundamentals of Programming Languages-II

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  1. Fundamentals of Programming Languages-II Subject Code: 110010 Teaching Scheme Examination Scheme Theory: 1 Hr./Week Online Examination: 50 Marks Practical: 2 Hrs./Week

  2. Unit-I Microprocessors and Micro-Controllers Architectures and Programming Concepts

  3. Microprocessors

  4. 1.1 Features of 386DX Microprocessors • It has 32-bit address bus and a 32-bit data bus. • It is a 32-bit processor. The 32-bit ALU allows to process 32-bit data. • It has 32-bit address bus. So it can access up to 4 Gbyte (232) physical memory or 64 terabyte(246) of virtual memory. • It runs with speed up to 20 Mhz instructions per second. • The pipelined architecture of the 80386DX, allows simultaneous instruction fetching, decoding, execution and memory management.

  5. It allows programmers to switch between different operating systems such as PC-DOS and UNIX. • It can operate on 17 different data types. • It has built-in virtual memory management circuitry and protection circuitry required to operate an 80386DX in these modes. • The 80386DX can operate in real mode, protected mode or a variation of protected mode called virtual 8086 mode.

  6. In real mode it functions basically as a fast 8086 or real mode 80286 • The 80386DX microprocessor is compatible with their earlier 8086, 8088, 80186, 80188, 80286 chips. Virtually anything that runs under these microprocessors will also run under the 80386.

  7. 1.2 Functional Block Diagram of 80386DX The internal architecture of 80386DX is divided into 3 sections • Central processing unit • Execution unit • Instruction decode unit • Memory management unit • Segmentation unit • Paging unit • Bus Control unit

  8. These units operate in parallel. Fetching, decoding, execution, memory management and bus accesses for several instructions are performed simultaneously. • This parallel operation is called pipelined instruction processing. • Execution Unit • The execution unit reads the instruction from the instruction queue and executes the instructions. It consists of three subunits: Control unit, data unit and protection test unit.

  9. Architecture of 80386 • Three Sections: • Bus Interface units • Central Processing Unit • Memory Management Unit

  10. Control unit: It contains microcode and special hardware. The microcode and special hardware allows 80386DX to reduce time required for execution of multiply and divide instructions. It also speeds the effective address calculation. • Data Unit: The data unit contains the ALU, eight 32-bit general purpose registers and a 64-bit barrel shifter. The barrel shifter is used for multiple bit shifts in one clock. Thus it increases the speed of all shift and rotate operations. The multiple/divide logic implements the bit-shift-rotate algorithms to complete the operations in minimum time.

  11. Protection test unit: The protection test unit checks for segmentation violations under the control of the microcode. • Instruction Decode Unit • The instruction decode unit takes instruction bytes from the code pre fetch queue and translates them into microcode. The decoded instructions are then stored in the instruction queue. They are passed to the control section for deriving the necessary control signals.

  12. Segmentation Unit • The segmentation unit translates logical addresses into linear addresses at the request of the execution unit. The segmentation unit compares the effective address for the length limit specified in the segment descriptor. The segment unit adds the segment base and the effective address to generate linear address. • Paging Unit • It organizes the physical memory in terms of pages of 4 Kbytes size each.

  13. Bus Control Unit • It communicates with the outside world. • It provides a full 32-bit bi-directional data bus and 32-bit address bus. • It controls the interface to external bus masters and coprocessors. • Instruction Pre fetch Unit • The instruction pre fetch unit fetches sequentially the instruction byte stream from the memory.

  14. MCQs • The 80386 is a _____ bit microprocessor. • 16 • 20 • 32 • 64 • The ALU of 80386 is _____ bit • 16 • 20 • 32 • 64

  15. The address bus of 80386DX is ___bit. • 16 • 32 • 20 • 64 • The 80386DX can address up to ___ physical memory. • 1 Mbytes • 16 Mbytes • 1 Gbytes • 4 Gbytes


  17. The steps performed by the computer processor for each machine language instruction received. The machine cycle is a 4 process cycle that includes reading and interpreting the machine language, executing the code and then storing that code.

  18. Four steps of Machine cycle • Fetch - Retrieve an instruction from the memory. • Decode - Translate the retrieved instruction into a series of computer commands. • Execute - Execute the computer commands. • Store - Send and write the results back in memory.

  19. 1.4 Memory types

  20. Memory Hierarchy • The memory unit is an essential component in any digital computer since it is needed for storing programs and data • Not all accumulated information is needed by the CPU at the same time • Therefore, it is more economical to use low-cost storage devices to serve as a backup for storing the information that is not currently used by CPU

  21. Memory Hierarchy • Computer Memory Hierarchy is a pyramid structure that is commonly used to illustrate the significant differences among memory types. • The memory unit that directly communicate with CPU is called the main memory • Devices that provide backup storage are called auxiliary memory • The memory hierarchy system consists of all storage devices employed in a computer system from the slow by high-capacity auxiliary memory to a relatively faster main memory, to an even smaller and faster cache memory

  22. MEMORY HIERARCHY Memory Hierarchy is to obtain the highest possible access speed while minimizing the total cost of the memory system Auxiliary memory Magnetic I/O Main tapes memory processor Magnetic disks Cache CPU memory Register Cache Main Memory Magnetic Disk Magnetic Tape

  23. Memory Hierarchy • The main memory occupies a central position by being able to communicate directly with the CPU and with auxiliary memory devices through an I/O processor • A special very-high-speed memory called cache is used to increase the speed of processing by making current programs and data available to the CPU at a rapid rate

  24. Memory Hierarchy • CPU logic is usually faster than main memory access time, with the result that processing speed is limited primarily by the speed of main memory • The cache is used for storing segments of programs currently being executed in the CPU and temporary data frequently needed in the present calculations • The typical access time ratio between cache and main memory is about 1to7 • Auxiliary memory access time is usually 1000 times that of main memory

  25. Main Memory • Most of the main memory in a general purpose computer is made up of RAM integrated circuits chips, but a portion of the memory may be constructed with ROM chips • RAM– Random Access memory • Integated RAM are available in two possible operating modes, Static and Dynamic • ROM– Read Only memory

  26. Main Memory • A RAM chip is better suited for communication with the CPU if it has one or more control inputs that select the chip when needed • The Block diagram of a RAM chip is shown next slide, the capacity of the memory is 128 words of 8 bits (one byte) per word

  27. RAM

  28. SRAM vs DRAM Summary Tran. Access per bit time Persist? Sensitive? Cost Applications SRAM 6 1X Yes No 100x cache memories DRAM 1 10X No Yes 1X Main memories, frame buffers

  29. RAM • Read/write memory, that initially doesn’t contain any data • The computing system that it is used in usually stores data at various locations to retrieve it latter from these locations • Its data pins are bidirectional (data can flow into or out of the chip via these pins), as opposite to those of ROM that are output only • It loses its data once the power is removed, so it is a volatile memory • It has a directional select signal R/W’; When R/W’=1, the chip outputs data to the rest of the circuit; when R/W’ = 0 it inputs data from the rest of the circuit

  30. Random-Access Memory Types • Static RAM (SRAM) • Each cell stores bit with a six-transistor (Diode) circuit. • Retains value indefinitely, as long as it is kept powered. • Relatively insensitive to disturbances such as electrical noise. • Faster and more expensive than DRAM. • Dynamic RAM (DRAM) • Each cell stores bit with a capacitor and transistor. • Value must be refreshed every 10-100 ms. • Sensitive to disturbances. • Slower and cheaper than SRAM.

  31. Random-Access Memory • Key features • RAM is packaged as a chip. • Basic storage unit is a cell (one bit per cell). • Multiple RAM chips form a memory. • Static RAM (SRAM) • Each cell stores bit with a six-transistor circuit. • Retains value indefinitely, as long as it is kept powered. • Relatively insensitive to disturbances such as electrical noise. • Faster and more expensive than DRAM. • Dynamic RAM (DRAM) • Each cell stores bit with a capacitor and transistor. • Value must be refreshed every 10-100 ms. • Sensitive to disturbances. • Slower and cheaper than SRAM.

  32. ROM • ROM is used for storing programs that are PERMENTLY resident in the computer and for tables of constants that do not change in value once the production of the computer is completed • The ROM portion of main memory is needed for storing an initial program called bootstrap loader, witch is to start the computer software operating when power is turned off

  33. ROM • Data is programmed into the chip using an external ROM programmer • The programmed chip is used as a component into the circuit • The circuit doesn’t change the content of the ROM • Can be used as lookup tables to implement various functions • Used by PCs to store the instructions that form their Basic Input/Output System (BIOS) • When power is removed from a ROM chip, the information is not lost, so it is a nonvolatile type of memory • It has a OE (Output Enable) specific control pin. Both OE and CE must be enabled in order for the ROM to output data; otherwise its data output is tri-stated.

  34. ROM Types • Masked ROM – programmed with its data when the chip is fabricated • PROM – programmable ROM, by the user using a standard PROM programmer, by burning some special type of fuses. Once programmed will not be possible to program it again • EPROM – erasable ROM; the chip can be erased and chip reprogrammed; programming process consists in charging some internal capacitors; the UV light (method of erase) makes those capacitors to leak their charge, thus resetting the chip • EEPROM – Electrically Erasable PROM; it is possible to modify individual locations of the memory, leaving others unchanged; one common use of the EEPROM is in BIOS of personal computers.

  35. ROM

  36. Nonvolatile Memories • DRAM and SRAM are volatile memories • Lose information if powered off. • Nonvolatile memories retain value even if powered off. • Generic name is read-only memory (ROM). • Misleading because some ROMs can be read and modified. • Types of ROMs • Programmable ROM (PROM) • Eraseable programmable ROM (EPROM) • Electrically eraseable PROM (EEPROM) • Flash memory • Firmware • Program stored in a ROM • Boot time code, BIOS (basic input/ouput system) • graphics cards, disk controllers.

  37. Auxiliary Memory • The main memory construction is costly. Therefore, it has to be limited in size. The main memory is used to store only those instructions and data which are to be used immediately. However, a computer has to store a large amount of information. The bulk of information is stored in the auxiliary memory. This is also called backing storageor secondary storage. They include hard disk, floppy disks, CD-ROM, USB flash drives, etc. • When the electricity supply to the computer is off, all data stored in the primary storage is destroyed. On the other hand, this is not true for secondary storage. The data stored in secondary storage can be stored for the desired time.

  38. Disk Geometry • Disks consist of platters, each with two surfaces. • Each surface consists of concentric rings called tracks. • Each track consists of sectors separated by gaps. tracks surface track k gaps spindle sectors

  39. Disk Geometry (Muliple-Platter View) • Aligned tracks form a cylinder. cylinder k surface 0 platter 0 surface 1 surface 2 platter 1 surface 3 surface 4 platter 2 surface 5 spindle

  40. Disk storage • Disks are used to store data, applications software and operating systems software. Whereas the primary form of storage in the early days of computing was magnetic tape, this has been replaced by predominantly disk based medium today. The reasons for this trend has been • decreasing cost per bit • reliability • reduced access times • higher transfer rates (more data per second) • reduced size and power requirements • increased capacity • One trend during the past few years is a move to optical storage medium. Many software companies offer both operating systems software and application software on optical medium (CDROM or DVDROM)

  41. Disk storage technology • Disk storage systems work on magnetic principles. • In magnetism, there are two opposing polarities called poles, the north and the South pole. Opposite polarity attracts, whilst like polarity repels. • In computers, data is represented in binary format. • Binary data has two states, a 1 or a 0. It just so happens that magnetism also has two states, north and south, so in effect, magnetism is a good way of storing data also • A rotating disk is coated with very fine ferrous oxide particles, each of which act and behave like little magnets • All that is required now is a mechanism of converting the digital data of 0's and 1's into magnetic states of north and south poles. • In a storage disk drive, the mechanism which performs the function of converting the digital 0's and 1's into magnetic states which can magnetize the surface areas of the disk is called the write head. A similar head, called the read head, is used to detect the magnetic states on the surface of the disk and convert them back into digital states

  42. Disk Capacity • Capacity: maximum number of bits that can be stored. • Vendors express capacity in units of gigabytes (GB), where 1 GB = 10^9. • Capacity is determined by these technology factors: • Recording density (bits/in): number of bits that can be squeezed into a 1 inch segment of a track. • Track density (tracks/in): number of tracks that can be squeezed into a 1 inch radial segment. • Areal density (bits/in2): product of recording and track density. • Modern disks partition tracks into disjoint subsets called recording zones • Each track in a zone has the same number of sectors, determined by the circumference of innermost track. • Each zone has a different number of sectors/track

  43. Computing Disk Capacity • Capacity = (# bytes/sector) x (avg. # sectors/track) x • (# tracks/surface) x (# surfaces/platter) x • (# platters/disk) • Example: • 512 bytes/sector • 300 sectors/track (on average) • 20,000 tracks/surface • 2 surfaces/platter • 5 platters/disk • Capacity = 512 x 300 x 20000 x 2 x 5 • = 30,720,000,000 • = 30.72 GB

  44. The read/write head is attached to the end of the arm and flies over the disk surface on a thin cushion of air. By moving radially, the arm can position the read/write head over any track. Disk Operation (Single-Platter View) The disk surface spins at a fixed rotational rate spindle spindle spindle spindle spindle

  45. Disk Operation (Multi-Platter View) read/write heads move in unison from cylinder to cylinder arm spindle

  46. Disk Access Time • Average time to access some target sector approximated by : • Taccess = Tavg seek + Tavg rotation + Tavg transfer • Seek time (Tavg seek) • Time to position heads over cylinder containing target sector. • Typical Tavg seek = 9 ms • Rotational latency (Tavg rotation) • Time waiting for first bit of target sector to pass under r/w head. • Tavg rotation = 1/2 x 1/RPMs x 60 sec/1 min • Transfer time (Tavg transfer) • Time to read the bits in the target sector. • Tavg transfer = 1/RPM x 1/(avg # sectors/track) x 60 secs/1 min.

  47. Disk Access Time Example • Given: • Rotational rate = 7,200 RPM • Average seek time = 9 ms. • Avg # sectors/track = 400. • Derived: • Tavg rotation = 1/2 x (60 secs/7200 RPM) x 1000 ms/sec = 4 ms. • Tavg transfer = 60/7200 RPM x 1/400 secs/track x 1000 ms/sec = 0.02 ms • Taccess = 9 ms + 4 ms + 0.02 ms • Important points: • Access time dominated by seek time and rotational latency. • First bit in a sector is the most expensive, the rest are free. • SRAM access time is about 4 ns/doubleword, DRAM about 60 ns • Disk is about 40,000 times slower than SRAM, • 2,500 times slower then DRAM.

  48. Optical Disks • The data is accessed from the underside of the CD-ROM. According to the initial specification devised by Philips and Sony, data is stored in a single track which is embedded into a polycarbonate material • The track starts at the inner of the disk, and ends at the outer radius of the disk. The track length is thus one long tightly wound spiral, the equivalent of over 3 miles long • The track is comprised of indentations or bumps which are created on a master disc. This master disc is then used to create the actual CDROM's which are shipped to customers. This technique is similar to the technique which was used to create audio records. • The laser beam is shone onto the surface of the disk. Data is stored as a sequence of surface variations called lands (flat surface) and pits (bumps or holes). The light is scattered by the pits and reflected by the lands. These two variations encode the binary 0's and 1's. The laser beam is moved to follow the spiral track of the data stored on the disk, detected the pits and lands as it follows the spiral track. • A light sensitive diode picks up the reflected laser light from the surface of the disk, and converts the light to digital data.