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University of Tehran Department of Electrical and Computer Engineering

University of Tehran Department of Electrical and Computer Engineering. ISSCC 2013 / SESSION 18 / ADVANCED EMBEDDED SRAM / 18.1 A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications. by : Milad Zamani May 2013. Contents. Introduction

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University of Tehran Department of Electrical and Computer Engineering

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  1. University of TehranDepartment of Electrical and Computer Engineering ISSCC 2013 / SESSION 18 / ADVANCED EMBEDDED SRAM / 18.1 A 20nm 112Mb SRAM in High-κ Metal-Gate with Assist Circuitry for Low-Leakage and Low-VMIN Applications by: MiladZamani May 2013

  2. Contents • Introduction • Proposed structure • Implementation & Layout • Conclusions Introduction Proposed structure Implementation & Layout Conclusions 1/17

  3. Introduction • SRAM Structure • Stability • Leakage Introduction SRAM Structure Stability Leakage 2/17

  4. SRAM Structure • Cell • Decoder • Sense Amplifier • Write Driver • Timing Introduction SRAM Structure Stability Leakage Jan M. Rabaey, Anantha P. handrakasan, Borivoje Nikolić, “Digital integrated circuits: a design perspective” , Prentice Hall; 2 edition, January 3, 2003. 3/17

  5. Stability • Static Noise Margin (SNM) Introduction SRAM Structure Stability Leakage Jan M. Rabaey, Anantha P. handrakasan, Borivoje Nikolić, “Digital integrated circuits: a design perspective” , Prentice Hall; 2 edition, January 3, 2003. 4/17

  6. Stability • Dynamic Noise Margin Introduction SRAM Structure Stability Leakage SengOonToh; ZhengGuo; Liu, T.-J.K.; Nikolic, B.; , "Characterization of Dynamic SRAM Stability in 45 nm CMOS," Solid-State Circuits, IEEE Journal of , vol.46, no.11, pp.2702-2712, Nov. 2011 5/17

  7. Subthreshold SRAM • Leakage Current Introduction SRAM Structure Stability Leakage Verma, N.; Chandrakasan, A.P.; , "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy," Solid-State Circuits, IEEE Journal of , vol.43, no.1, pp.141-149, Jan. 2008 6/17

  8. Proposed structure • Proposed Circuit • partially suppressed wordline (PSWL) scheme and bitline-length-tracked negative-bitline-boosting (BT-NBL) scheme • Power management Proposed Circuit PSWL & BT-NBL Power management 7/17

  9. Proposed structure Proposed Circuit PSWL & BT-NBL Power management Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  8/17

  10. Proposed structure Proposed Circuit PSWL & BT-NBL Power management Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  9/17

  11. Proposed structure Proposed Circuit PSWL & BT-NBL Power management Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  10/17

  12. Implementation & Layout • Structure • layout Structure layout 11/17

  13. Implementation & Layout Structure layout 12/17

  14. Implementation & Layout Structure layout Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  13/17

  15. The die area of the test-chip is 40.3mm2 with 448 (2048×134) SRAM macros Implementation & Layout Structure layout Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  14/17

  16. With the SD, PSD and DR power-management modes, the SRAM leakage current is reduced to 16.6% for full macro shut down, 44.7% of peripheral circuits shut down and 34.2% for the peripheral circuits shut down with arrays entering into data-retention mode • Nothing about stability !!! Conclusion 15/16

  17. Trends Trends 16/17

  18. Trends Trends 17/17

  19. Refrence • Jan M. Rabaey, Anantha P. handrakasan, BorivojeNikolić, “Digital integrated circuits: a design perspective” , Prentice Hall; 2 edition, January 3, 2003. • SengOonToh; ZhengGuo; Liu, T.-J.K.; Nikolic, B.; , "Characterization of Dynamic SRAM Stability in 45 nm CMOS," Solid-State Circuits, IEEE Journal of , vol.46, no.11, pp.2702-2712, Nov. 2011 • Verma, N.; Chandrakasan, A.P.; , "A 256 kb 65 nm 8T Subthreshold SRAM Employing Sense-Amplifier Redundancy," Solid-State Circuits, IEEE Journal of , vol.43, no.1, pp.141-149, Jan. 2008 • Chang, Jonathan; Chen, Yen-Huei; Cheng, Hank; Chan, Wei-Min; Liao, Hung-Jen; Li, Quincy; Chang, Stanley; Natarajan, Sreedhar; Lee, Robin; Wang, Ping-Wei; Lin, Shyue-Shyh; Wu, Chung-Cheng; Cheng, Kuan-Lun; Cao, Min; Chang, George H., "A 20nm 112Mb SRAM in High-к metal-gate with assist circuitry for low-leakage and low-VMIN applications," Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2013  • Trends in ISSCC 2013

  20. Thanks for your attention

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