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Understanding Parallel Computers

This comprehensive overview explores the intricacies of parallel computers and processing. It discusses the importance of machine architecture knowledge for developers, particularly game developers, embedded systems, and hardware vendors. Key topics include balancing coding specific to different machines, the lifetime and performance goals, and the necessity of portability. The text delves into various parallel computer designs, such as Chip Multiprocessors, Intel Core Duo, and BlueGene/L supercomputers, emphasizing their unique characteristics and implementations.

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Understanding Parallel Computers

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  1. Understanding Parallel Computers Parallel ProcessingEE 613

  2. Balancing Machine Specifics With Portability • How much do we need to know about the machine architecture • Performance goal • Game developers, embedded systems, and hardware vendors • Coding specific to machine • Lifetime goal • Portability • Generalized code

  3. A Look At Six Parallel Computers • Chip Multiprocessors • Intel Core Duo • AMD Dual Core Opteron • Heterogeneous Chip Designs • GPU, FPGA, Cell • Vector • Clusters • Node – processors, RAM, disk, memory not shared • Typical - eight nodes, control processor, switch • Blade server – includes com ports and cooling fans • Supercomputers – BlueGene/L (440 PowerPC’s)

  4. CSE524 Parallel Algorithms Lawrence Snyder

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  8. Now we can put multiple cores on a single chip. CSE524 Parallel Algorithms Lawrence Snyder

  9. MESI – Modified, Exclusive, Shared, Invalid CSE524 Parallel Algorithms Lawrence Snyder

  10. CSE524 Parallel Algorithms Lawrence Snyder

  11. MOESI – Modified, Owned, Exclusive, Shared, Invalid CSE524 Parallel Algorithms Lawrence Snyder

  12. Both designs implement a coherent shared memory. CSE524 Parallel Algorithms Lawrence Snyder

  13. CSE524 Parallel Algorithms Lawrence Snyder

  14. Symmetric Multiprocessor (SMP) • Each processor makes memory requests over the common memory bus • All cache controllers snoop the memory bus and adjust the tags on their cached values to ensure coherent cache usage.

  15. Example – po & p1 have copies of Block X, but p2 writes to Block X. CSE524 Parallel Algorithms Lawrence Snyder

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