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Overview of Memory Addressing Modes and Load Instructions in CISC Microcontrollers

DESCRIPTION

This overview highlights the key aspects of memory addressing modes and load instructions related to CISC microcontrollers. It details the usage of various instructions including DECA and DECB, as well as decrementing memory operations. The text emphasizes different addressing modes like Extended, Indexed, and Direct Addressing while citing relevant pages from the textbook. It also notes crucial OpCodes, execution bytes, and cycles required, illustrating the complexities of loading memory into 8-bit registers with instructions such as LDAA, LDAB, and others.

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Overview of Memory Addressing Modes and Load Instructions in CISC Microcontrollers

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Presentation Transcript

  1. Instruction Set Overview

  2. CLRA, CLRB • Chart from pg 483 of textbook • Note: OpCode, Number of bytes, cycles to execute • Note: Sets & Resets some condition codes

  3. DECA, DECB, DEC memory (pg 483) Dec memory supports different addressing modes: EXT means Extended – the entire 16-bit memory address is included in the instruction IND, X - Indexed Addressing (pg 75), using the X index register, and an 8-bit offset to create the effective address. Note the number of additional cycles required: the memory must be loaded, decremented and stored back to memory. This shows that our microcontroller is a CISC computer.

  4. Load Instructions LDAA & LDAB load memory to 8-bit registers. Multiple addressing modes: IMM – Immediate, load a constant DIR – Direct Addressing, uses an address, but the upper byte is always 00 – so is usable only for a small range of memory.

  5. STAA, STAB, STD

  6. ANDA, ANDB

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