Limits on Adiabatics: Friction, Leakage, & Clock/Power Supplies

1. Physical Limits of ComputingDr. Mike Frank CIS 6930, Sec. #3753XSpring 2002 Lecture #25Limits on Adiabatics: Friction, Leakage, & Clock/Power SuppliesFri., Mar. 15

2. Administrivia & Overview • Don’t forget to keep up with homework! • We are 8 out of 14 weeks into the course. • You should have earned ~57 points by now. • Course outline: • Part I&II, Background, Fundamental Limits - done • Part III, Future of Semiconductor Technology - done • Part IV, Potential Future Computing Technologies - done • Part V, Classical Reversible Computing • Adiabatic electronics & CMOS logic families, - last Mon. & Wed • Limits of adiabatics: Friction,Leakage,Power supplies. Fri.,TODAY • RevComp theory I: Emulating Irreversible Machines - TODAY • RevComp theory II: Bounds on Space-Time Overheads - Wed. 3/20 • Physics-based models of computing - Fri. 3/22 • (plus ~6 more lectures…) • Part VI, Quantum Computing • Part VII, Cosmological Limits, Wrap-Up

3. Limits of Adiabatics II:Leakage (wrap-up)

4. Leakage in CMOS • (See transparencies - not electronic yet.) • In a given technology with constant-field scaling, leakage becomes worse at small scales because: • Energy barriers between states are lower • Higher rates of thermally-induced leakage, at given T • Higher rates of quantum tunnelling (temp.-independent) • Energy barriers between states are narrower • Higher rates of quantum tunnelling • These effects get worse exponentially with 1/length (doubly-exponentially with time) • Need alt. technologies w. high energy barriers!

5. Future Techs. w. Low Leakage? • How can achieve low entropy coefficients in minimum-scale (atomic-scale) devices? • Need high energy barriers: • Can achieve with atomic (not just electronic) interactions: • E.g. mechanical logics (rod logic, buckling logic) • If strong bonds (e.g. C-C) are used in structure, rates of unwanted bond breakage can made be very low. • Rate for an atom passing through another one (e.g. knobs in rod logic) is extremely low due to • height of barrier: strength of Coulombic & fermionic repulsion between electrons, & • width of barrier: large number of particles involved • Other possibilities?

6. Limits of Adiabatics III:Clock/Power Supplies See transparencies.

7. Timing in Adiabatic Systems When multiple adiabatic devices interact, the relative timing must be precise, in order to ensure that adiabatic rules are met. • There are two basic approaches to timing: • Global (a.k.a. clocked, a.k.a. synchronous) timing • Approach in nearly all conventional irreversible CPUs • Basis for all practical adiabatic/quantum computing mechanisms proposed to date • Local (a.k.a. self-timed, a.k.a. asynchronous) timing • Implemented in a few commercial irreversible chips. • Feynman ‘86 showed a self-timed serial reversible computation was implementable in QM, in principle • Margolus ‘90 extended this to a 2-D model with 1-D of parallelism. - Will it work in 3-D?

8. Global Timing • Examples of adiabatic systems designed on the basis of global, synchronous timing: • Adiabatic CMOS with external power/clock rails • Superconducting parametric quantron (Likharev) • Adiabatic Quantum-Dot Cellular Automaton (Lent) • Adiabatic mechanical logics (Merkle, Drexler) • All proposed quantum computers • But, a problem: Synchronous timing may not scale! • Work by Janzig & others raises issues of possible limits due to quantum uncertainty. Unresolved.

9. Clock/Power Supply Desiderata • Requirements for an adiabatic timing signal / power supply: • Generate trapezoidal waveform with very flat high/low regions • Flatness limits Q of logic. • Waveform during transitions is ideally linear, • But this does not affect maximum Q, only energy coefficient. • Operate resonantly with logic, with high Q. • Power supply Q will limit overall system Q • Reasonable cost, compared to logic it powers. • If possible, scale Q t (cycle time) • Required to be considered an adiabatic mechanism. • May conflict w. inductor scaling laws! • At the least, Q should be high at leakage-limited speed (Ideally,independentof t.)

10. Supply concepts in my research • Superpose several sinusoidal signals from phase-synchronized oscillators at harmonics of fundamental frequency • Weight these frequency components as per Fourier transform of desired waveform • Create relatively high-L integrated inductors via vertical, helical metal coils • Only thin oxide layers between turns • Use mechanically oscillating, capacitive MEMS structures in vacuo as high-Q (~10k) oscillator • Use geometry to get desired wave shape directly

11. Early supply concepts • Inductors & switches. • See transparency. • Stepwise charging. • See transparency.

12. Newer Supply Concepts • Transmission-line-based adiabatic resonators. • See transparency. • MEMS-based resonant power supply • See transparency, & next slide • Ideal adiabatic supplies - Can they exist? • Idealized mechanical model: See transparency. • But, may be quantum limits to reusability/scalability of global timing signals. • This is a very fundamental issue!

13. A MEMS Supply Concept • Energy storedmechanically. • Variable couplingstrength -> customwave shape. • Can reduce lossesthrough balancing,filtering. • Issue: How toadjust frequency?

14. Summary of Limiting Factors When considering adiabaticizing a system: • What fraction of system power is in logic? fL • Vs. Displays, transmitters, propulsion. • What fraction of logic is done adiabatically? fa • Can be all, but w. cost-efficiency overheads. • How large is the Ion/Ioff ratio of switches? • Affects leakage & minimum adiabatic energy. • What is the Qsup of the resonant power supply? • What is the relative cost of power & logic? r$ • E.g. decreasing power cost by r$ by increasingHW cost by  r$ will not help. “Power premium”

15. Min. energy & Roff/Ron ratio • Note that:cE = C2V2Ronand if dominant leakage is source/drain:Pleak = V2/Roff • So:cEPleak = C2V4/(Roff/Ron)Emin = 2(cEPleak)1/2 = 2CV2(Roff/Ron)1/2 • So:Qmax = ½CV2 / (2CV2(Roff/Ron)1/2) = ¼(Roff/Ron)1/2= ¼(Ion/Ioff)1/2

16. Minimizing cost/performance • $P = Cost of power in original system • $H = Cost of logic HW in original system • $P = r$$H; $H = $P/r$ • For cost-efficiency inverse to energy savings: • $tot,min = $Pr$-1/2 + $Hr$1/2 = 2 $Pr$-1/2 • $tot,orig = $P + $H = (1+r$)$H = ((1+r$)/r$) $P • $tot,orig/$tot,min = ½(1+r$)r$-1/2 ½r$1/2 for large r$

17. Summary of adiabatic limits • Cost-effective adiabatic energy savings factor: Sa = Econv / Eadia in cost-effective adiabatic system • Some rough upper bounds on Sa:Sa ~ 1/(1fL)Sa ~ 1/(1fa)Sa ~ ¼(Ion/Ioff)1/2Sa  QsupSa  ~ r$1/2 (worse for non-ideal apps) • Discussion ignores benefits from adiabatics of denser packing & smaller communications delays in parallel algorithms. (More later.)

18. Reversible Computing Theory I:Reversible Logic Models

19. Reversible Logic Models • It is useful to have a logic-level (Boolean) model of adiabatic circuits. • Can model all logic using pipelinable logic elements that consume their inputs. • Warning: In such models Memory requires recirculation! This is not necessarily more energy-efficient in practice than retractile (non-input consuming) approaches! • There is a need for more flexible logic models. • If inputs are consumed, then inputoutput logic function must be invertible.

20. Input-consuming inverter: Before: After:inoutinout0 - - 1 1 - - 0E.g. SCRL implementation: in out Input arrow indicates inputdata is consumed by element.

21. An Irreversible Consuming Gate • Input-consuming NAND gate: Before: After:ABoutABout 0 0 - - - 1 0 1 - 1 0 - - - 0 1 1 - • No implementation in SCRL (or any fully adiabatic style) as a stand-alone, pipelined logic element! A out B 4 possible inputs, 2possible outputs. At least 2 of the 4 possibleinput cases must lead todissipation!

22. NAND w. 1 input copied? • Still not invertible: Before AfterABA’outABA’out 0 0 - - - - 0 1 0 1 - - - - 1 1 1 0 - - - - 1 0 1 1 - - A’ A out B

23. Reversible Computing Theory II:Emulating Irreversible Machines