The Role of EDA in SoC Design

1. The Role of EDA in SoC Design HKSTP International Technology Conference January 14, 2003 Dr. Chi-Foon Chan President and Chief Operating Officer Synopsys, Inc.

2. Agenda • Economic • Technical Challenges • Methodology

3. Agenda • Economic Challenges • Technical Challenges • Methodology

4. EDA $2.5B Design Mask Data Masks $2.1B Front-End $22B Materials $4.2B Back-End $5.9B Semiconductor Value Flow in 1996 Systems $851B Embedded SW $0.4B IP $0.3B Fabless $10B IDM $122B Manufacturing Foundry $5.4B Various sources Aprox. Values for 2001

5. EDA $3.6B Design Mask Data Masks $2.3B Front-End $24B Materials $4.0B Back-End $5.6B Semiconductor Value Flow in 2001 Systems $1050B Embedded SW $0.8B IP $0.9B Fabless $13B IDM $106B Manufacturing Foundry $9.1B Various sources Aprox. Values for 2001

6. EDA $6.1B Design Mask Data Masks $3.7B Front-End $31B Materials $6.7B Back-End $10B Semiconductor Value Flow in 2006 Systems $1429B Embedded SW $1.7B IP $1.8B Fabless $52B IDM $122B Manufacturing Foundry $31B Various sources Aprox. Values for 2001

7. Semiconductor Sales Downturn 1989 1985 1989 1998 1996 1998 1996 1985 October 2002 2002 9/01 Source: SIA WSTS 3-mos average, Synopsys

8. Semiconductor Sales Downturn 1989 1985 1998 1996 2002 9/01 Source: SIA WSTS 3-mos average, Synopsys

9. Semiconductor Sales Downturn 1989 1985 1998 1996 October 2002 Source: SIA WSTS 3-mos average, Synopsys

10. Semiconductor Sales Downturn Asia Pacific Percent of Peak Month Sales Worldwide Source: SIA WSTS, Synopsys

11. Average: $10M+, 300+ Staff-months! Escalating Development Costs and Time Sample (Actual) VDSM Projects Source: International Business Strategies, 2002

12. Flow Tools IP Blocks Libraries Process Fab Process Sophistication Leads to Complex Alliances

13. Semiconductor Partnerships

14. Agenda • Economic Overview • Technical Challenges • Methodology

15. In £ 0.18u Wire-to-Wire Cap Dominates (CW >> CS) CW CS £ 0.25m Less Charge Diode Drains Charge M3 M1 M2 M1 Metal 3 Jumper Reduces Metal 1 L Deep Subm Creates Many Problems Interconnect Delay • Signal Integrity • Crosstalk • Capacitive coupling • Inductive coupling • IR (voltage) Drop • Reliability • Electromigration • Hot electron device degradation • Manufacturability • Process antenna effect (PAE) • Minimum area rule (MAE) • Double cut via • End-of-line wire extension • Metal filling / wide wire slotting

16. Large, Complex Chips Timing Closure Bus Interface IP A/D, D/A MPEG PLL Signal Integrity CDI Memory Control Sync R A M Manufacturability Arbiter Challenges in Design Implementation

17. > 200B Simulation Cycles Simulation Cycles 10T 2007 Gates 100B 2001 More Tools and Larger Verification Teams 100M 1995 Design 30% 1M 10M 100M 70% Verification Growing Verification Complexity Lines of Code > 1M lines of HDL code! 1980 2002

18. Average Gate Counts By Region Designs tend to be larger in North America (more mP) and tend to be smaller in Asia (more consumer electronics) Synopsys SNUG Data 2002

19. Most Non-North America Chips Run at <150MHz Synopsys SNUG Data 2002

20. Design Geometries by Region 44% of designs in Asia at .25-micron or larger compared to 22% in Japan and 17% in Europe Synopsys SNUG Data 2002

21. Most Non-North America Chips Run at <150MHz Synopsys SNUG Data 2002

22. Synthesis Physical Power Test IP Customers Will Increasingly Converge on Platforms Architecture Design Design Planning Verification IP Languages Assertions and Testbenches Design Database Timing and Signal Integrity Physical Implementation Smart Verification Extraction Physical Verification Mixed Signal / Analog Mask Synthesis / OPC Implementation Platform Verification Platform

23. Agenda • Economic • Technical Challenges • Methodology

24. Complexity Physics Design Pressures Courtesy of NVIDIA

25. Solutions Higher level of abstraction System-level tools IP design reuse 2000 EY 2007 200 EY 2001 20 EY 1995 100M Gates 10M Gates 1M Gates Challenge: HW/SW Complexity

26. 95% 80% Customer Designed 50% 2000 2005 2010 … 80% of the circuitry in SoCswill be acquired, not designed By 2005.. 3rd Party IP Star IP In-house IP

27. IP is at the core of deep sub-micron SoC design methodology • Platforms = IP + SLD (HW)

28. Creating & integrating quality IP Changing the corporate culture IP Reuse: 3 Fundamental Hurdles Efficiently acquiring 3rd-party IP

29. Design using integrated platform of tools Choose solid IP partners IP Reuse: 3 Solutions Start right: Use “top down” methodology

30. Agenda • Economic • Technical Challenges • Methodology

31. Craft advantageous economic ventures Current Realities of IC Design Economic Stress Design Challenge Increasing Complexity Solution = Smart Partnerships • Partner with EDA to overcome technical challenges • Use “partnered” tools: platforms and IP deal with shrinking geometries and increasing complexities

32. 2002 EE Times Reader EDA Survey Attribute in selecting vendor Importance Best after-sales support 66% Best integration w/ other vendors’ tools 47% Technology leader today 45% Technology leader in 3 years 41% Clear vision of future 34% Best documentation 34% Most ethical company 30% Best training services 22% Knowledgeable sales reps 21% Well-managed company 20% Best before-sales system support 12% Offers consulting design services 9% Best Web site 8%

33. Design