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Arithmetic for Computer

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  1. Arithmetic for Computer

  2. ALU Register A Flags Register Register B Function Control Arithmetic & Logic Unit • Does the calculations • Everything else in the computer is there to service this unit • Handles integers • May handle floating point (real) numbers • May be separate FPU (maths co-processor) • May be on chip separate FPU (486DX +) ALU Inputs and Outputs Arithmetic for Computers

  3. Arithmetic Unit Adder Subtracter MUX Multiplier MUX Y Divider Logic Unit Operation Y = A + B Y = A – B Y = A x B Y = A / B Y = A ^ B Y = A V B Y = ~ A Y = A + B Comments Add Subtract Multiply Divide AND OR NOT XOR C2C1C0 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 AND OR MUX NOT XOR n n n n n n n n n n n n n C2 C0C1 A B Arithmetic Logic Unit Arithmetic for Computers

  4. Introduction (§3.1) • Bits are just bits (no inherent meaning)— conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number • How do we represent negative numbers? i.e., which bit patterns will represent which numbers? Arithmetic for Computers

  5. Integer Representation (§3.2) • Only have 0 & 1 to represent everything • Positive numbers stored in binary • e.g. 41=00101001 • No minus sign • No period • Sign-Magnitude • Left most bit is sign bit • 0 means positive • +18 = 00010010 • 1 means negative • -18 = 10010010 • Problems • Need to consider both sign and magnitude in arithmetic • Two representations of zero (+0 and -0) • Two’s compliment Arithmetic for Computers

  6. Possible Representations • Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations • Which one is best? Why? Arithmetic for Computers

  7. maxint minint MIPS • 32 bit signed numbers:0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten...0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0000two = 0ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten...1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten Arithmetic for Computers

  8. Two's Complement Operations • Negating a two's complement number: invert all bits and add 1 • remember: “negate” and “invert” are quite different! • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • "sign extension" (lbu vs. lb) Arithmetic for Computers

  9. Addition & Subtraction (§3.3) • Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 • Two's complement operations easy • subtraction using addition of negative numbers 0111 + 1010 • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed” Arithmetic for Computers

  10. Detecting Overflow • No overflow when adding a positive and a negative number • No overflow when signs are the same for subtraction • Overflow occurs when the value affects the sign: • overflow when adding two positives yields a negative • or, adding two negatives gives a positive • or, subtract a negative from a positive and get a negative • or, subtract a positive from a negative and get a positive • Consider the operations A + B, and A – B • Can overflow occur if B is 0 ? • Can overflow occur if A is 0 ? Arithmetic for Computers

  11. Effects of Overflow • An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details based on software system / language • example: flight control vs. homework assignment • Don't always want to detect overflow— new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons Arithmetic for Computers

  12. Ci-1 AiBiCi-1 SiCi 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 Ai Ci Bi Ci-1 Si Ci-1 Ci-1 Ai Full Adder Si Bi Ai Bi Si Ci Cinput A0 B0 Full Adder S0 Cinput A An-1 … A1A0 B Bn-1 … B1B0 S Sn-1 … S1S0 C0 + + Cin Cin n n n N-bit Parallel (Ripple Carry) Adder A A1 B1 Cout Cout Full Adder S1 S B C1 Ci Coutput An-1 Bn-1 Full Adder Sn-1 Coutput Parallel (Ripple Carry) Adder • Full Adder Arithmetic for Computers

  13. Fully Parallel Adder • The fastest adder design would be strictly parallel. • All the inputs would be applied simultaneously and propagate through two levels of logic to obtain the result. • Consider the generation of the carry bits • These equations can be simplified into the sum of products form, allowing each to be realized with two levels of logic, independent of the word width of the adder Arithmetic for Computers

  14. g2 p1 g1 p0 g0 Ai Bi Ci-1 A0 B0 A1 B1 Cin A2 B2 Adder Adder Adder S2 S1 S0 CLA Adder Carry Look Ahead (CLA) Circuit C0 C1 Cout pi C2 C0 C1 gi Si Carry Look Ahead Adder Arithmetic for Computers

  15. A B n 1 1 n n n n 1 N-bit Adder Select Cout Cin Function S = A + B S = A - B Select 0 1 Carry S Two’s Complement Adder/Subtracter • Subtraction in the two’s complement number system is performed as follows: (S)2 = (A)2– (B)2 = (A)2 + (-B)2 = (A)2 + [B]2 = (A)2 + (B)2 + 1 Arithmetic for Computers

  16. B Register A Register Complementer 0 1 addition/subtraction CF Adder OF Hardware for Addition and Subtraction Arithmetic for Computers

  17. Gate Carry Input Operation Input1 1-bit Full Adder MUX Result Input2 Carry Output 1-bit ALU Arithmetic for Computers

  18. Gate Operation 3 3 3 3 Input10 1-bit ALU Result0 Input20 Input11 1-bit ALU Result1 Input21 Input130 1-bit ALU Result30 Input230 Input131 1-bit ALU Result31 Input231 Zero Overflow Carry Output 32-Bit ALU Arithmetic for Computers

  19. Multiplicand 10002 Multiplier 10012 1000 00000 000000 1000000 Product 10010002 x + Multiplication (§3.4) • More complicated than addition • accomplished via shifting and addition • Multiplying 10002 by 10012 Arithmetic for Computers

  20. P0 Pi-1 Pi Pn-1 =P where, (2iX) is equivalent to X shifting i positions to the left. Multiplication : Algorithm I Therefore, Multiplication is implemented by 1. Shifting X by yi bit at a time, 2. Adding the resulting terms. Arithmetic for Computers

  21. LSB=1 Test LSB of Multiplier LSB=0 2. Addition; Add Multiplicand to Product in ALU, And place the result in Product Register 1. Shifting; Shift the Multiplicand Register left 1 bit Shift the Multiplier Register right 1 bit repetition < n ? yes no Multiplication : Algorithm I 0. Initialization; Load Multiplicand and Multiplier, And Clear Product and iteration Arithmetic for Computers

  22. 0. Initialization; X input1; Y input2; P 0; iteration 0; BEGIN init X input1; Y input2; P 0; iteration 0; next if (Ylsb=1) { add P P + X; } shift X shift-left X; Y shift-right Y; iteration++; if (iteration<n) goto next; end output P; Ylsb=1 Ylsb 2. Addition; P P + X; Ylsb=0 1. Shifting; X shift-left X; Y shift-right Y; iteration++; yes iteration < n ? no END Multiplication : Algorithm I Arithmetic for Computers

  23. Iteration 0 0 1 0 3 1 0 4 3 0 1 3 3 2 1 2 2 1 2 Increment Repetition & Check Increment Repetition & Check Increment Repetition & Check Increment Repetition & Check Shift Left Multiplicand Shift Left Multiplicand Shift Left Multiplicand Shift Left Multiplicand Shift Right Multiplier Shift Right Multiplier Shift Right Multiplier Shift Right Multiplier Initial values Test of LSB Test of LSB Test of LSB Test of LSB Operation Addition Addition Multiplier 0001 0001 0000 0001 0000 0000 0000 0000 0001 0000 0011 0000 0000 0000 0011 0000 0001 0011 0011 Multiplicand 0001 0000 0000 0100 0000 0100 0010 0000 0000 1000 0001 0000 0000 1000 0010 0000 0000 0010 0000 1000 0001 0000 0000 0100 0000 0010 0000 0010 0000 0100 0000 0100 0010 0000 0001 0000 0000 1000 0000 0110 0000 0110 0000 0010 0000 0110 0000 0010 0000 0110 0000 0010 0000 0110 0000 0110 0000 0000 0000 0110 0000 0010 0000 0000 0000 0110 0000 0110 0000 0010 0000 0110 0000 0110 0000 0110 Product Multiplication : Example • Multiply 210 x 310, or 00102 x 00112 Arithmetic for Computers

  24. input1 input2 Y input2; X input1; init X input1; Y input2; P 0; iteration 0; next if (Ylsb=1) { add P P + X; } shift X shift-left X; Y shift-right Y; iteration++; if (iteration<n) goto next; end output P; Load Y X Y sr Y; Load X sl X; ShiftRight ShiftLeft Ylsb + Add Control Unit P P + X; Load P iteration Increment Clear Clear P 0; iter iteration 0; output P; output Multiplication : Implementation I Arithmetic for Computers

  25. Input2 Input1 0 n n n Load Multiplicand X Shift Left 2n 2n 2n 2n 2n Load Multiplier Y Shift Right Add 2n-bit ALU Ylsb Control Unit Load Product P Clear iteration Clear Counter C Increment Output Multiplication : Implementation I Arithmetic for Computers

  26. Multiplication : Algorithm II Therefore, Multiplication is implemented by 1. Adding the high of product with X by yi, 2. Shifting the resulting terms. Arithmetic for Computers

  27. Test LSB of Multiplier LSB=1 LSB=0 1. Addition; Add Multiplicand to the high of Product, And place the result in the high of Product Register 2. Shifting; Shift the Product Register right1 bit Shift the Multiplier Register right 1 bit repetition < n ? yes no Multiplication : Algorithm II 0. Initialization; Load Multiplicand and Multiplier, And Clear Product and iteration Arithmetic for Computers

  28. 0. Initialization; X input1; Y input2; P 0; iteration 0; BEGIN init X input1; Y input2; P 0; iteration 0; next if (Ylsb=1) { add PH PH + X; } shift P shift-right P; Y shift-right Y; iteration++; if (iteration<n) goto next; end output [P]; Ylsb=1 Ylsb 1. Addition; PH PH + X; Ylsb=0 2. Shifting; P shift-right P; Y shift-right Y; iteration++; yes iteration < n ? no END Multiplication : Algorithm II Arithmetic for Computers

  29. Iteration 0 0 1 0 3 1 0 4 3 0 1 3 3 2 1 2 2 1 2 Increment Repetition & Check Increment Repetition & Check Increment Repetition & Check Increment Repetition & Check Shift Right Multiplier Shift Right Multiplier Shift Right Multiplier Shift Right Multiplier Shift Right Product Shift Right Product Shift Right Product Shift Right Product Initial values Test of LSB Test of LSB Test of LSB Test of LSB Operation Addition Addition Multiplier 0001 0001 0000 0001 0000 0000 0000 0000 0001 0000 0011 0000 0000 0000 0011 0000 0001 0011 0011 Multiplicand 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0010 0001 1000 0001 1000 0001 0000 0011 0000 0010 0000 0000 0110 0001 0000 0000 1100 0000 1100 0000 0000 0001 1000 0001 0000 0000 0000 0000 0110 0000 0110 0001 0000 0000 1100 0001 1000 0000 1100 Product Multiplication : Example • Multiply 210 x 310 = 610, or 00102 x 00112 = 01102 Arithmetic for Computers

  30. Input2 Input1 n n n n n n n Multiplicand X Load Load Multiplier Y n bit ALU Shift Right Add Ylsb Load Control Unit Shift Right Product P Clear iteration 2n Clear Counter C Increment Output Multiplication : Implementation II Arithmetic for Computers

  31. 0. Initialization; Load Multiplicand, Load Multiplier to the low of Product Register, And Clear the high of Product, and iteration Test LSB of Multiplier LSB=1 LSB=0 1. Addition; Add Multiplicand to the high of Product, And place the result in the high of Product Register 2. Shifting; Shift the Product Register right 1 bit repetition < n ? yes no Multiplication : Algorithm III • Multiplier = the low of Product Register Arithmetic for Computers

  32. BEGIN 0. Initialization; X input1; PL input2; PH 0; iteration 0; init X input1; PL input2; PH 0; iteration 0; next if (Plsb=1) { add PH PH + X; } shift P shift-right P; iteration++; if (iteration<n) goto next; end output P; Plsb=1 Plsb 1. Addition; PH PH + X; Plsb=0 2. Shifting; P shift-right P; iteration++; yes iteration < n ? no END Multiplication : Algorithm III Arithmetic for Computers

  33. Iteration Operation Multiplicand Product 0 Initial values 0010 0000 0011 0 Test of LSB 0010 0000 0011 0 Addition 0010 0010 0011 0 Shift Right Product 0010 0001 0001 1 Increment Repetition & Check 0010 0001 0001 1 Test of LSB 0010 0001 0001 1 Addition 0010 0011 0001 1 Shift Right Product 0010 0001 1000 2 Increment Repetition & Check 0010 0001 1000 2 Test of LSB 0010 0001 1000 2 Shift Right Product 0010 0000 1100 3 Increment Repetition & Check 0010 0000 1100 3 Test of LSB 0010 0000 1100 3 Shift Right Product 0010 0000 0110 4 Increment Repetition & Check 0010 0000 0110 Multiplication : Example • Multiply 210 x 310 = 610, or 00102 x 00112 = 01102 Arithmetic for Computers

  34. Input2 Input1 n n n n n n n Multiplicand X Load n bit ALU Add Load Load Control Unit Product (PH) P (PL) Shift Right iteration Clear Clear Plsb 2n Counter C Increment Output Multiplication : Implementation III Arithmetic for Computers

  35. Two’s Complement Multiplication Arithmetic for Computers

  36. BEGIN init X input1; PL input2; PH 0; iteration 0; loop if (Plsb=1) { add PH PH + X; } shift P shift-right[P]; iteration++; if (iteration<n-1) goto loop; if (Plsb=1) { sub PH PH - X; } shift P shift-right[P]; end output P; 0. Initialization; X input1; PL input2; PH 0; iteration 0; Plsb=1 Plsb Plsb=0 3. Subtraction; PH PH - X; 1. Addition; PH PH + X; iteration++; yes 2. Shifting; P shift-right P; 4. Shifting; P shift-right P; iteration < n-1 ? Plsb=1 no Plsb Plsb=0 END Two’s Complement Multiplication Arithmetic for Computers

  37. Two’s Complement Multiplication • Example: Multiply 210 x (-3)10,=(-6)10, or 00102 x 11012 = 1111 10102 Arithmetic for Computers

  38. Input2 Input1 n n n n n n n Multiplicand X Load n bit ALU Add Sub Load Load Control Unit Shift Right F Product (PH) P (PL) iteration Clear Clear Plsb Counter C 2n Increment Output Two’s Complement Multiplication Arithmetic for Computers

  39. n-1 j j-1 i i-1 0 Y= 0...00011111…11100000…0 = 2j - 2i Booth’s Algorithm • A more elegant approach to multiplying signed number Ex. 001110=24 - 21=16 - 2=14 P = X x Y = X x (2j - 2i) = 2jX - 2iX Arithmetic for Computers

  40. Booth’s Algorithm • Example: Multiply 210 x 310, or 00102 x 00112 Arithmetic for Computers

  41. Booth’s Algorithm • Example: Multiply 210 x (-3)10, or 00102 x 11012 Arithmetic for Computers

  42. BEGIN 0. Initialization; X input1; PL input2; PH 0; iteration 0; 01 10 Plsb,P-1 1a. Addition; PH PH + X; 1b. Subtraction; PH PH - X; 00,11 2. Shifting; P shift-right P; iteration++; yes iteration < n ? no END Booth’s Algorithm Arithmetic for Computers

  43. Input2 Input1 n n n n n n Multiplicand X Load n bit ALU Add Sub Load Load Control Unit Shift Right Product (PH) P (PL) P-1 F iteration Clear P-1 Clear 2n Counter C Plsb Increment Output Booth’s Algorithm : Implementation Arithmetic for Computers

  44. Initialization S0 / Xload,PLload, PHclear, Cclear; no BEGIN yes 01 10 Plsb,P-1 Subtraction Addition 00,11 S2 / PHload,Sub; S1 / PHload,Add; Shifting S3 / Pshift-right; Cincrement; yes [C] < n ? no END Booth’s Algorithm : Control Design • Control Signal Arithmetic for Computers

  45. Present State BEGIN ([C]<n) Plsb P-l Next State Xload PLload PHclear PHload Pshift-right Add Sub C-clear C-increment END JK-Flip-Flop Inputs S0 S1 S2 S3 00 00 00 00 00 01 10 11 11 11 11 11 0 d d d 1 d 0 0 1 d 0 1 1 d 1 0 1 d 1 1 d d d d d d d d d 0 d d d 1 0 0 d 1 0 1 d 1 1 0 d 1 1 1 Booth’s Algorithm : Control Design • Transition Table 0d 0d 1d 0d 0d 1d 1d 1d 1d 0d 1d d0 d0 1d d1 d1 d0 d1 d1 d0 d0 d0 d0 d1 00 11 01 10 11 11 11 00 10 01 11 10 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 0 1 0 Arithmetic for Computers

  46. Booth’s Algorithm : Control Design • Logic Function : J1 Arithmetic for Computers

  47. Booth’s Algorithm : Control Design • Logic Function Arithmetic for Computers

  48. Xload PLload PHclear Cclear PHload Add Pshift-right C-increment END Combinational Logic BEGIN Plsb P-1 ([C]<n) y1 ~y1 y0 ~y0 J1 K1 J0 K0 JK-Flip Flops clock Control Design : State-table Method • Logic Diagram Arithmetic for Computers

  49. Arithmetic for Computers

  50. Arithmetic for Computers