Computer Systems Organization & Architecture Chapter 1 Part 6 Registers

1. Computer Systems Organization & Architecture Chapter 1 Part 6 Registers

2. Register • A register is a sequential circuit that can be set to a specific state and retain that state until externally changed. • State is a combination of bits

3. Register Design • An S-R latch is a simple 1-bit register. • With (S)et input, latch output can be set to 1 • With (R)eset input, latch output can be set to 0.

4. Register Design • A D flip-flop can be used as a 1-bit register • Input 0, output is set to 0 when flip-flop is clocked • Input 1, output is set to 1 when flip-flop clocked • Can consider the clock to be a load signal. • On rising edge of load signal, the data on D input line is stored in the flip-flop

5. d inputs c b a • Da Dd Dc Db Ck Qd Ck Qa Ck Qb Ck Qa load outputs d c b a Multibit Register • Use multiple flip-flops. Each stores a single bit. • Common load signal.

6. Shift Registers • Sometimes data is received one bit at a time (serially) • Example • 4 bits come in one bit at a time • least significant bit first • clock signal goes high when each bit is available • receiving circuit needs to perform serial-to-parallel conversion

7. Shift Registerserial-in parallel-out • Dd input to first flip-flop is the serial line in. • data in for each additional flip-flop is the data out of the previous flip-flop. • bit-available line runs to the clock input on each flip-flop. When high, each flip-flop loads its input value. serial in • Da Dd Dc Db Ck Qd Ck Qa Ck Qb Ck Qa bit available outputs d c b a

8. Shift Registers • How do we perform serial output? • Use parallel-in serial-out shift register. • Parallel input could come from a parallel data bus • Parallel input could come from a serial-in parallel-out shift register

9. Shift Register parallel-in serial-out • Input of each flip-flop could come from parallel load or from previous flip-flop • use 2-to-1mux to determine where input comes from parallel inputs c d b a ~SHIFT/LOAD • Da 2-to-1 mux 2-to-1 mux 2-to-1 mux 2-to-1 mux Dd Dc Db serial input Ck Qd Ck Qa Ck Qb Ck Qa clock serial out shift if ~SHIFT/LOAD line is low parallel load if ~SHIFT/LOAD line is high

10. Shift Register parallel-in serial-out • To serially transmit a 4-bit word • ~SHIFT/LOAD line set high • 4-bit value loaded into the register on the first clock cycle • The least significant bit is now available at Qa (the output line). • Before the next clock cycle, the ~SHIFT/LOAD line is returned low • on successive clock cycles the 4-bit value is shifted right • next bit is then available on output line

11. Transparent Latches • Registers so far: • values are stored on a clock or load signal • outputs change only when a new value loaded on the clock edge • Transparent latch • has gate or enable input • when enabled, outputs of the latch directly follow the inputs of the latch • the latch is “transparent” (except for small propagation delay) • when not enabled, outputs remain in same state. • similar to S-R gated latch

12. Transparent Latches • Applications • to reduce number of pins on a chip, multiplex data lines with address lines • same pins used for both • during one half of a master clock cycle, pins represent the address • during second half, same pins represent the data lines. • use transparent latch to keep address values during second half of clock cycle • during first half the latches are enabled, receive address values • during second half, latches are disabled, keep the value of the address • Will see an example when we examine RAM.

13. Register Interfacing • How do registers interface with CPU? • Assume • CPU has 16-bit address bus • use decoder to enable proper register • based on the address, decoder enables proper register • Assume when CPU addresses the register, an enable line for the register will go low. • Call this the ~ENABLE line.

14. Register Interfacing • Assume • ~READ line goes low when CPU reads from the addressed register • ~WRITE line goes low when CPU writes to the addressed register • There is a master clock signal, MCLK • All lines become valid during the low half of the MCLK cycle. • CPU reads data from the data bus on the falling edge of MCLK • Data from CPU is valid on the falling edge of MCLK

15. Register Interfacing MCLK Address (ENABLE) READ, WRITE valid Data read, written data valid

16. Interfacing a Write-Only Reg • Applications: • outputs of a 8-bit register used to run 8 indicator LEDs • microprocessor lights any combination of LEDs by storing different values in the register. • microprocessor only writes to the register

17. Interfacing a Write-Only Reg • Concern: when to load the register with the data on the data bus. • ~WRITE goes low • ~ENABLE goes low • on falling edge of MCLK, register should load data. • registers we have seen load data on rising edge of their clock; we will use a special LOAD line to register • LOAD must rise when MCLK falls to load register • see next slide

18. Interfacing a Write-Only Reg MCLK ~WRITE ~READ LOAD Rising edge loads data

19. Interfacing a Write-Only Reg • Creating the circuit for LOAD: • if ~WRITE and ~ENABLE are low and MCLK is high, then LOAD should go low. • when MCLK returns low, LOAD must go high to generate a rising edge to load the register • see next slide

20. Interfacing a Write-Only Reg Generation of the LOAD signal MCLK LOAD ~ENABLE ~WRITE

21. Interfacing a Read-Only Reg • Applications • External event stores a value in the register for later reading by the microprocessor • Example:keyboard-encoding circuit for a numeric keypad • Circuit converts a key closure into a binary value representing the key pressed • Stores this value in a register • Signals the microprocessor that a new key value is available. • Microprocessor will then read the value.

22. Interfacing a Read-Only Reg • Interface • Outputs of a register (I.e., of flip-flops) always available • Want to selectively read register when outputs are always on • Data bus • When CPU is writing, its outputs drive the data bus • No other device can put a value on the data bus • When CPU is reading, only the outputs of the addressed device are driving the data bus • The only time the outputs of a device are connected to the data bus is when the CPU is reading the device

23. Interfacing a Read-Only Reg • Recall tri-state gates or buffers • Output can be 1, 0, or disconnected • To control disconnected, has an enable line • Can get active-low and active-high tri-state devices

24. Interfacing a Read-Only Reg serial out inputs d c b a • Da Dd Dc Db Ck Qd Ck Qa Ck Qb Ck Qa load output enable outputs d c b a

25. Interfacing a Read-Only Reg • Last slide: 4-bit register with tristate gates at outputs • Active-low enable • When enable line is high, register is disconnected from data bus

26. Interfacing a Read-Only Reg • Interfacing to data bus • When ~READ line goes low • And ~ENABLE line goes low (address on bus is for this register) • Outputs of register must be connected to the data bus before the falling edge of MLCK • This is when the CPU reads the value of the bus.

27. Interfacing a Read-Only Reg MCLK CPU reads data bus On falling edge of MCLK ~READ ~ENABLE Output enable Outputs connected to data bus While output enable is low

28. MCLK Output Enable ~ENABLE ~Read Interfacing a Read-Only Reg Generation of the Output-Enable signal

29. Interfacing a Read/Write Reg • Example: general purpose register • Register is both read and written to • Just combine the read-only and write-only solutions.

30. Register Files Register Files are a set of registers that can be read/written by supplying a register number.

31. Reading a Register

32. Writing a Register MCLK

33. Reading/Writing a Register • What happens if we read and write a register on the same clock cycle? • The value returned from the read will be the value that was stored earlier. • The value written will overwrite the current value only after the current value is read. • If want to read the value that is being written must add logic to the register file. • Will do this later when we talk about control.