Presentation 24 – Computer Memory

1. Presentation 24 – Computer Memory

2. Objectives At the end of this presentation, you will be able to:

3. Compare and contrast the following types of memory: RAM, SRAM, DRAM, SDRAM, VRAM, ROM, PROM, EPROM, and EEPROM. • Explain the difference between volatile and non-volatile memory. • Explain the purpose of cache memory. • Compare and contrast the following types of memory: SIMMs, DIMMS, DDR, and DDR2. • Demonstrate the proper method to uninstall and reinstall a single-inline memory module (DIMM). • Demonstrate the proper method to uninstall and reinstall a dual-inline memory module (DIMM).

4. Describe the characteristics of the following types of memory and server memory requirements: • Memory Interleaving • ECC • Hardware Compatibility List • Define the following cache memories and explain how they work: • Processor cache • Disk cache • Explain the precautions required when upgrading memory.

5. Define virtual memory. • Define cache, cache hit, and cache miss. • Explain how disk caching improves performance. • Describe the Least Recently Used (LRU) cache algorithm, explain how it works, and list several applications in which it is most effective. • Describe the Read Ahead cache algorithm, explain how it works, and list several applications in which it is most effective.

6. RAM…Random Access Memory • Volatility • Refresh • Access Speed • Packaging

7. Static RAM…SRAM • No Refresh • Fast • More expensive

8. Dynamic RAM…DRAM • Needs refreshed • Fairly fast • Inexpensive • Small

9. DRAM “forgets” • Each DRAM bit is made up of a transistor and a capacitor. • Small capacitors lose their charge over time • Capacitors must be recharged

10. Full charge Charge (volts) Minimum charge Time

11. Circuit loses its charge slowly Charge Refresh Refresh Refresh Refresh Time Refresh boosts the charge

12. EDO RAM • Newer technology • Faster than standard DRAM • Slightly more expensive

13. Synchronous DRAM… SDRAM • Runs at the same speed as the main system bus. • Should be matched to the bus speed. • Used in P2, P3, and some P4 systems

14. Programmable Read-Only Memory...PROM • Non-Volatile • Slow • Difficult to Change • Expensive

15. Erasable PROM… EPROM

16. Electrically-Erasable PROM… EEPROM

17. 72-pin SIMM

18. DIMM

19. Double Data Rate (DDR) DIMM

20. DDR2 DIMM

21. Video RAM (VRAM)Windows RAM (WRAM)MDRAMSGRAM

22. Memory for Portables

23. Cache Memory

24. Centering Notch Notched End Rotate SIMM to about 45º 45º

25. Press SIMM into socket Push straight in

26. Rotate SIMM to the vertical position

27. Retaining clips Alignment pin

28. AMIBIOS System Configuration (C) 1985-1995, American Megatrends Inc., Main Processor : Pentium(P54C) Math Processor : Built-In Floppy Drive A: : 1.44 MB 3½” Floppy Drive B: : None AMIBIOS Date : 07/15/95 Processor Clock : 100MHz Power Management : Disabled Base Memory Size: 640KB Ext. Memory Size : 15360KB Display Type : VGA/EGA Serial Port(s) : 3F8,3E8 Parallel Port(s) : 378 External Cache : 256KB,Enabled Base Memory Size : 640KB Ext. Memory Size : 15360KB Plug and Play ISA Devices: Analog Devices AD1816 Bank 0: EDO Bank 1: FP Pci Devices: PCI Onboard IDE PCI Slot 2 VGA: IRQ 11 Bank 0: EDO Bank 1: FP

29. Installing DIMMs Notch Notch

30. DIMM Latch

32. Removing the DIMM

33. USB Flash Memory

34. DRAM vs. SRAM... • DRAM must be continually refreshed or it loses its memory. • DRAM is slow but inexpensive. • SRAM is fast, does not require refreshing, and holds its memory until power is removed. • SRAM is expensive.

35. Interleaving • Refreshing can be made more efficient by a memory design technique called Interleaving. • With Interleaving, memory is organized in banks. While a memory address in one bank is being refreshed, data is being retrieved from a memory address in another bank. • One stage gets the data from an address in a bank while at the same time the other stage refreshes an address in another bank.

36. Column 1 2 3 4 5 6 7 8 Row 1 Row 2 Row 3 Row 4 Row 5 Row 6 Memory Organization

37. Fast Page Mode (FPM) DRAM • Memory is arranged into pages of from 512 to several kilobytes each. • All data on the page can then be accessed without relocating the page. • As long as the next piece of data needed is on the selected page, it can be accessed directly without going through the hassle of relocating the page.

38. With EDO memory, the processor takes the same time to make the first data access as it would with DRAM. But once the EDO RAM finds that first piece of data, it can send nearby bytes to the processor very quickly. EDO (Extended Data Out) RAM

39. Synchronous DRAM • Synchronous means that the DRAM and processor use the same clock. When the processor needs data, SDRAM can have it ready. • SDRAM may also use pipelines. One stage fetches the next memory address while another stage outputs data. continued...

40. Synchronous DRAM (continued)... • SDRAM has a burst counter that increments column addresses and speeds up burst accesses when next data is in the same row. • SDRAM goes to the memory address the processor wants and sends that data to the processor. It then continues “shooting” data from the memory locations after that to the processor until the processor says to quit.

41. Synchronous DRAM (continued)... • Operates at speeds of 100 MHz and 133 MHZ. • Operates at the full width of the processors data bus. That is 64-bits (or 8 bytes) in the case of the Pentium. • Overall throughput is: • 8 bytes times 100MHz = 800 MB/sec • 8 bytes times 133MHz = 1 GB/sec • 8 bytes times 266MHz = 2 GB/sec • 8 bytes times 532MHz = 4 GB/sec • 8 bytes times 1066MHz = 8.5 GB/sec

42. Rambus DRAM (RDRAM) • Radically different memory design. • It transfers only 16 bits (2 bytes) at a time, but at a much higher speeds, typically 800MHz. • Throughput: • 2 bytes times 800MHz = 1.6 GB/sec

43. Error Correction Code (ECC) • Corrects single bit errors. • Detects, but cannot correct, 2-bit, 3-bit, and 4-bit errors. • Appends 8 additional bits on to every 64-bit double word in main memory. • The additional ECC bits are automatically generated and stored along with the original 64 bits.

44. Error Correction Code (ECC) • Later when the information is read back, the ECC bits are checked to make certain the information is still correct. • Memory with ECC protection is more expensive. • There is a slight speed penalty since some time is required to compute and then check the extra bits.

45. Speed Size 0.5ns CPU Registers <1kB 0.5ns 32kB L1 Cache 1ns 2MB L2 Cache 50ns 1GB System Memory 10 millisecs Virtual Memory (Disk) 1TB 100 millisecs Multiple Terabyte Network Virtual Memory

46. Virtual Memory • Allows the Operating System (OS) to use disk space as if it were an extension of RAM. • Data can be swapped in and out of RAM from the disk. • It allows the maximum size of programs and data to be limited only by the combined size of both physical memory and available disk space.

47. Caching – The technique of storing frequently-used or soon-to-be-needed data in high-speed memory so that it can be accessed more quickly.

48. Types of Caches • High-speed memory caches that operate faster than normal system memory. • Disk caches using solid state memory that operates faster than disk drives. • Internet caches using disk drives that operate faster than Internet delivery.

49. Processor Cache • Level 1 or L1 cache – A small high speed memory cache that is built into the CPU core itself. • Level 2 or L2 cache – A high speed memory cache that is located outside the CPU core, but usually inside the same package as the CPU core. Typically, it is located as close as possible to the CPU. It is larger but slower than the L1 cache.

50. The CPU Die L1 Cache Core L2 Cache