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Digital Circuit Toolbox: Verilog Hierarchy, Tristate Logic, and State Machines

This toolbox provides comprehensive guidance on using Verilog for digital circuit design, focusing on hierarchy creation for design identification, tristate signals, and internal busses. The documentation explains the implementation of priority encoders and state machines, including Moore and Mealy styles, converting between binary and Gray codes, and efficient state assignments. It also covers adders (half and full) and combinational multipliers, detailing how synthesis tools optimize logic implementation through structured designs. Explore how these components enhance FPGA designs.

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Digital Circuit Toolbox: Verilog Hierarchy, Tristate Logic, and State Machines

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Presentation Transcript

  1. A Digital Circuit Toolbox

  2. Verilog Hierarchy • Each design identifier creates a new branch of the hierarchy tree

  3. Tristate Signals and Busses • Tristate busses are allowed by most FPGA architectures on devices output pins • If tristate are not allowed, the synthesis may have control to automatically substitutes with MUXes

  4. Schematics for Internal Tristate Buffer Design

  5. MUX version of Tristate Buffer Design

  6. Bidirectional Busses • The signals is divided into two parts: the driver part input part • The two parts are then wired together

  7. Bidirectional Busses

  8. If/else Priority Encoder • Implied priority with precedence assigned to the first instruction encountered in a begin/end block

  9. If/else Priority Encoder

  10. Case Priority Encoder • The cases are mutually exclusive and do not overlap

  11. State Machines • Use a set of registers, to determine current machine state • Moore style : the output depends only on the state • Mealy style: the output depends on the state and some input signals

  12. State Machines

  13. State Machines

  14. Converting Binary to Gray Code

  15. Converting Gray Code to Binary

  16. State Assignment • Make a big difference in how efficiently your logic will be synthesize • use parameters, ‘define and ‘ifdef to select between encoding assignments

  17. State Assignment • One-hot state assignment means that each state is assigned a single state flip-flop which is active only in the assigned state • One-could state assignment means that a flip-flop is inactive only in the assigned state

  18. AddersHalf-Adder • The synthesis tool will examine each instance of the + operator and will try to implement the logic with a preoptimized module

  19. Half-Adder

  20. Full Adder • To turn the half adder into a full adder, we take the output of a half adder and connect it into another half adder

  21. Full Adder

  22. Full Adder

  23. Full Adder

  24. Subtractor • Similar to the adder

  25. Full-Subtractor

  26. Hard-Wired Multipliers • Multiply value by a constant • The multiplication process shifts and adds

  27. Generic Multipliers • We must create logic which allows all the shift and adds to be used

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